參考文獻 |
References
Chapter 1 Introduction
[1.1] intel 10nm technology leadership, Kaizad Mistry, Technology Symposium, April, pp.8, 2017.
[1.2] Moore, Gordon E. (1965-04-19). "Cramming more components onto integrated circuits". Electronics. Retrieved 2016.
[1.3] Tahir Ghani, “Innovative Device Structures and New Materials for Scaling Nano-CMOS Logic Transistors to the Limit”, intel, VLSI Symposium, 2000.
[1.4] Wiley, "CMOS: Circuit Design, Layout, and Simulation", IEEE, ISBN 978-0-470-88132-3. pp. 177-178, 2010.
[1.5] Varian Semiconductor Equipment Associates, IMP Process vs. Device Performance, Technology Symposium, Jan. 2008.
[1.6] Tahir Ghani, “22nm-Announcement Presentation”, intel, IEDM, 2011.
[1.7] 施敏原著,黃調元譯,半導體元件物理與製作技術,第二版,國立交通大學出版社, ISBN 957-30151-3-7, 2002.
[1.8] 李世鴻譯,Neamen原著,半導體物理與元件,Mc Grawhill,台商圖書, ISBN 957-493-719-4.
[1.9] 陳志芳教授,半導體原理及應用,國立成功大學電機工程學系,2006.
[1.10] 孫允武教授,半導體物理與元件,國立中興大學物理系.
[1.11] 張勁燕,深次微米製程技術,第四章,五南出版,2003,ISBN 957-11-2828-7.
[1.12] 羅正忠,張鼎張譯,半導體製程技術概論,1998.
[1.13] 王志明,半導體元件物理,正修科技大學,電機工程系.
[1.14] Junction Field-Effect Devices, Semiconductor Devices for Power Conditioning, 1982.
[1.15] Computer History Museum, “Metal Oxide Semiconductor (MOS) Transistor Demonstrated”, The Silicon Engine, 1960.
[1.16] Jacob Millman, Electronic devices and circuits. Singapore: McGraw-Hill International. ISBN 0-07-085505-6, 1985.
[1.17] G. E. Moore, “No Exponential is Forever: But "Forever" Can be Delayed!” IEEE ISSCC Tech. Digest , pp.20-23, 2003.
[1.18] W. Haensch et al. "Silicon CMOS Devices Beyond Scaling," IBM Journal of Research and Development, vol.50, no. 4/5, pp. 339-361, 2006.
[1.19] C. Y. Chang and S.M. Sze, ULSI Technology, McGraw-Hill International Editions, 2000, ISBN 0-07-114105-7.
[1.20] International Technology Roadmap for Semiconductor 2.0, Executive Report, , pp. 33 – 34, 2015.
[1.21] Chris Hobbs et al., “Advanced and Emerging Devices: SEMATECH’s Perspective”, SEMATECH Symposium, Tokyo, June 26, 2012.
[1.22] R. Dennard et al. “1990’s: Golden Era of Scaling Dramatic Vcc, Tox & Lg scaling. Increasing Idsat”, IEEE JSSC, 1974.
[1.23] Chia Hong Jan, “RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC (System-on-Chip) Applications”, intel Corp, IEDM, San Francisco, 2010.
[1.24] R. Dennard et al. IEEE JSSC, 1974.
[1.25] M. Fischetti et al., Journal of Applied Physics, 2001.
[1.26] M. Radosavlijevic et al., intel Corp, 2011.
[1.27] Applied Materials, “The Applications of Plasma Nitridation and Hi-K Metal Gate”, IEEE, 2010.
[1.28] Abhisek Dixit, et al., “Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs”, IEEE Transaction on electron devices, vol.52, No.6, JUNE 2005.
[1.29] International Technology Roadmap for Semiconductor 2.0, 2016.
[1.30] Ian Young, “The Impact of MOSFET Extrinsic R, C Parasitics and Potential Solutions”, Short Course, IEDM, 2011.
[1.31] Wallence Peng, “New Materials and Process Technologies for Scaling Nano CMOS”, Technology Symposium, Jan. 2013.
[1.32] Chang Yang Kang et al., “Advanced CMOS Scaling,” Sematech Smposium, Oct. 2011.
[1.33] Rahul Deokar et al., FinFET challenges and solutions – custom, digital, and signoff, Cadence Design Systems, EETimes, April 2013.
[1.34] Hisamoto, D. et al., "Impact of the vertical SOI ′DELTA′ structure on planar device technology", IEEE Transactions on Electronic Devices., vol. 6, pp.1419–1424, 2016.
[1.35] Hisamoto, D. et al. "Impact of the vertical SOI ′Delta′ Structure on Planar Device Technology", IEEE Transactions on Electronic Dev., vol.41, pp. 745, 1991.
[1.36] Chenming Hu et al. "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm", IEEE Transactions on Electron Devices., vol.47, pp.2320–2325, 2000.
[1.37] Min-hwa Chi, “Challenges in Manufacturing FinFET at 20nm node and Beyond”, Technology Symposium, TD, Globalfoundries, 2013.
[1.38] K. Kuhn, IEEE TED,vol. 59, No. 7, pp.1813 - 1827, July 2012.
[1.39]Rahul Kapoor et al., “技術互相依賴性以及半導體微影技術的演進”,中文半導體技術雜誌,第82期, Dec. 2008/ Jan. 2009.
[1.40] 莊達人,VLSI製造技術,高立圖書有限公司,ISBN 957-584-985, 2003.
[1.41] 劉柏村教授,薄膜沉積技術,交通大學光電工程學系.
[1.42] Wallence Peng, “New Materials and Process Technologies for Scaling Nano CMOS”, Technology Symposium, Jan. 2013.
[1.43] R. J. Mears, “以矽晶通道工程來取捨功率性能”,中文半導體技術雜誌,第81期,Nov. /Dec 2008.
[1.44] DieterK. Schroder, 3rd Edition, Semiconductor Material and Device Characterization, Wiley Interscience, ISBN 0-471-73906-5.
[1.45] Suvi Haukka et al., “Atomic Layer CVD for Production of 0.13 to 0.1 Micron Devices”, Technology Symposium, ASM Microchemistry Co. Ltd., Finland.
[1.46] T. Suntola, Atomic Layer Epitaxy, Handbook of Crystal Growth 3, Thin Films and Epitaxy, Part B: Growth Mechanisms and Dynamics, Chapter 14, Elsevier, 1994.
[1.47] Tsu‐Jae King Liu, “FinFET History, Fundamentals and Future”, University of California, Berkeley , VLSI Symposium, 2012.
[1.48] Kah-Wee Ang, Towards 3-Dimensional CMOS Scaling, Sematech Symposium, June, 2011.
[1.49] Suvi Haukka, “Atomic Layer CVD for Production of 0.13 to 0.1 Micron Devices”, Technology Symposium, ASM Microchemistry Co. Ltd., Finland.
[1.50] E. P. Gusev ta al., Appl. Phys. Lett. 2000.
[1.51] M. Leskelä and L. Niinistö, Atomic Layer Epitaxy, T. Suntola and M. Simpson (eds.), Blackie, London, 1990.
[1.52] 李朱育、李敏鴻、李勝偉、柯文政、段生振、陳念波,圖解光電半導體元件,ISBN 978-957-11-7477-8, 2014.
Chapter 2 Analysis of Contact Resistance Reduction
[2.1] Mehmet C. Ozturk, “Source/Drain Junctions and Contacts for 45 nm CMOS and Beyond”, Department of Electrical and Computer Engineering, North Carolina State University, International Conference on Characterization and Metrology for ULSI Technology, 2005.
[2.2] ITRI Roadmap, International Technology Roadmap for Semiconductor 2.0.
[2.3] Chang Yong Kang et al., “Advanced CMOS Scaling”, Sematech Symposium, Korea, October 27-28, 2011.
[2.4] Abhisek Dixit et al., “Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs”, IEEE Transaction on electron devices, vol.52, No. 6, June 2005.
[2.5] Ian Young, “The Impact of MOSFET Extrinsic R, C Parasitics and Potential Solutions”, Short Course, IEDM, 2011.
[2.6] Pankaj Kalra, “Advanced Source/Drain Technologies for Nanoscale CMOS, Engineering”, Electrical Engineering and Computer Sciences, University of California, Berkeley.
[2.7] S. D. Kim et al., "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part I: Theoretical Derivation", IEEE Transactions on Electron Devices, vol.49, pp.457-466, 2002.
[2.8] S. D. Kim et al., "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime—Part II: Quantitative Analysis", IEEE Transactions on Electron Devices, vol.49, pp.467-472, 2002.
[2.9] Stanford University, Metal/Semiconductor Ohmic Contacts, https://web.stanford.edu, 1999.
[2.10] Richard B. Fair, “Rapid Thermal Processing Science and technology”, Edited by Academic Press Inc., 1250 Sixth Avenue San Diego, CA 92101-4311, 1993.
[2.11] R.W. Mann et al., “The C49 to C54 phase transformation in TiSi2 thin films”, Journal of Electrochem. Society, vol.141, pp.1347-1350, 1994.
[2.12] G.L. Miles et al., “TiSi2 phase transformation characteristics on narrow devices”, Thin Solid Films, vol.290, pp.469-472, 1996.
[2.13] A. Lauwers et al., “TiCo bilayers in salicide technology: electrical evaluation”, Applied Surf. Sci. vol.91, pp.12-18, 1995.
[2.14] J.A. Kittl et al., “Salicides: materials, scaling and manufacturability issues for future integrated circuits (invited)”, Microelectronic Engineering, vol.50, pp.87-101, 2000.
[2.15] M. Diale et al., “Cobalt self‐diffusion during cobalt silicide growth”, Applied Physics, Lett., vol.62, pp.943-945, 1993.
[2.16] E.G. Colgan et al., “Formation and stability of silicides on polycrystalline silicon”, Material Science Engineering, vol.16, pp.43-96, 1996.
[2.17] C.J. Choi et al., “Thickness effect of a Ge interlayer on the formation of nickel silicides”, Journal of Electrochem. Soc., vol.154, pp.759-763, 2007.
[2.18] S.W. Lee et al., “C redistribution during Ni silicide formation on Si1-yCy epitaxial layers”, Journal Electrochem. Soc., vol.157, pp. 97-300, 2010.
[2.19] A. Lauwers1 et al., Technology Symposium, Belgium, 2002.
[2.20] Eun-Ha Kim1 et al., “Ni2Si and NiSi Formation by Low Temperature Soak and Spike RTPs”, Technology Symposium, Standford University, 2005.
[2.21] C. Lavoie et al., “Effects of additives on the phase formation and morphological stability of nickel monosilicide films”, Microelectronic Engineering, vol.83, pp.2042-2054, 2006.
[2.22] C. Boulord et al., “Electrical and structural characterization of electroless nickel–phosphorus contacts for silicon solar cell metallization semiconductor devices, materials, and processing”, J. Electrochem. Soc., vol.157, pp.742-745, 2010.
[2.23] X.P. Qu et al., “Thermal stability, phase and interface uniformity of Ni-silicide formed by Ni-Si solid-state reaction”, Thin Solid Films, vol.462, pp.146-150, 2004.
[2.24] J. Demeulemeester et al., “Pt redistribution during Ni(Pt) silicide formation”, Appl. Phys. Lett., vol.93, pp. 261-262, 2008.
[2.25] D. Lee et al., “The effects of Ta on the formation of Ni-silicide in Ni0.95xTa0.05x/Si systems”, Material Science Engineering, vol.114, pp.241-245 2004.
[2.26] Y. Setiawan et al., “Effect of Ti alloying in nickel silicide formation”, Thin Solid Films, vol.504, pp.153-156, 2006.
[2.27] F. Allenstein et al., “Influence of Al on the growth of NiSi2 on Si(001)”, Microelectronic Engineering, vol.82, pp.474-478, 2005.
[2.28] K. Tsutsui et al., “Improvement of thermal stability of Ni silicide on N+-Si by direct deposition of group III element (Al, B) thin film at Ni/Si interface”, Microelectronic Engineering, vol.85, pp.2000-2004, 2008.
[2.29] J. Luo, Y.L. Jiang, G.P. Ru, B.Z. Li, P.K. Chu, Silicidation of Ni(Yb) film on Si(001), J. Electron. Mater., vol.37, pp.245-248, 2008.
[2.30] W. Huang et al., “The improvement of thermal stability of nickel silicide by adding a thin Zr interlayer”, Microelectron. Engineering, vol.83, pp.345-350, 2006.
[2.31] W. Huang et al., “Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi”, Microelectron. Eng., vol.84, pp.678-683, 2007.
[2.32] W. Huang et al., “Effect of erbium interlayer on nickel silicide formation on Si(100)”, Appl. Surf. Sci., vol.254, pp.2120-2123, 2008.
[2.33] A.S.W. Wong et al., “F-enhanced morphological and thermal stability of NiSi films on BF2+-implanted Si(001)”, Applied Physics Letter, vol.81, pp.5138-5140, 2002.
[2.34] P.S. Lee et al., “Improved NiSi salicide process using presilicide N2+ implant for MOSFETs”, IEEE Electron Device Letter, vol.21, pp.566-568, 2000.
[2.35] B.Y. Tsui et al., “Improvement of the thermal stability of NiSi by germanium ion implantation”, Journal of Electrochemistry Society, vol.157, pp.137-143, 2010.
[2.36] O. Nakatsuka et al., “Improvement in NiSi/Si contact properties with C-implantation”, Microelectronic Engineering, vol.82, pp.479-484, 2005.
[2.37] N. Variam et al., “The contact engineering with ion implantation”, Technology Symposium, 2013.
Chapter 3 Influence of Al addition on phase transformation and thermal stability of nickel silicides on Si (001)
[3.1] A. Lauwers et al., “Ni based silicides for 45 nm CMOS and beyond, Material Science Engineering, vol.B, pp.114–115, 2004.
[3.2] M. Sinha et al., “Novel aluminum segregation at NiSi/p+-Si source/drain contact for drive current enhancement in p-channel FinFETs”, IEEE Electron Devices Letter, vol.30, pp.85-87, 2009.
[3.3] Z. Zhang et al., “Exploitation of a self-limiting process for reproducible formation of ultrathin Ni1−xPtx silicide films”, Applied Physics Letter, vol.97, 252108, 2010.
[3.4] C.J. Choi et al., “Thickness effect of a Ge interlayer on the formation of nickel silicides” Journal of Electrochem. Society, vol.154, pp.759-763, 2007.
[3.5] S.W. Lee et al., “C redistribution during Ni silicide formation on Si1-yCy epitaxial layers”, Journal of Electrochem. Society, vol.157, pp.297-300, 2010.
[3.6] C. Boulord et al., “Electrical and structural characterization of electroless nickel–phosphorus contacts for silicon solar cell metallization”, J Journal of Electrochem. Society. vol.157, pp.742-745, 2010.
[3.7] K.D. Keyser et al., “Phase formation and thermal stability of ultrathin nickel-silicides on Si(100)”, Appl. Phys. Lett., vol.96, 173503, 2010.
[3.8] K.R. Lee et al., “Thermal stability of Ni(Ta) silicide films on ultra-thin silicon-on-insulator substrates”, Journal of Alloys and Compounds, in press, 2010.
[3.9] K. Hoummada et al., “Effect of Pt addition on Ni silicide formation at low temperature: Growth, redistribution, and solubility, Journal of Applied Physics, vol.106, 063511, 2003.
[3.10] D. Deduytsche, et al. “Influence of Pt addition on the texture of NiSi on Si(001)”, Appl. Phys. Lett., vol.84, pp.3549-3551, 2004.
[3.11] J. Demeulemeester et al., “Pt redistribution during Ni(Pt) silicide formation”, Appl. Phys. Lett., vol.93, 261912, 2008.
[3.12] D. Mangelinck et al., “Enhancement of thermal stability of NiSi films on (100)Si and (111)Si by Pt addition”, Appl. Phys. Lett., vol.75, pp.1736-1738, 1999.
[3.13] D. Deduytsche et al., “Formation and morphological stability of NiSi in the presence of W, Ti, and Ta alloying elements”, Journal of Applied Physics, vol.101, 044508, 2007.
[3.14] S.L. Chiu et.al., “ Effects of Ti interlayer on Ni/Si reaction systems”, J. Electrochem. Soc., vol.157, G452-G455, 2004.
[3.15] P. Gergaud et al., “Stresses arising from a solid state reaction between palladium films and Si(001) investigated by in situ combined x-ray diffraction and curvature measurements”, J. Appl. Phys., vol.94, pp.1584-1591, 2003.
[3.16] M. Chan et al., “Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance”, IEEE Trans. Electron Devices, vol.15, pp.22-24, 1994.
[3.17] E. Alptekin et al., “Schottky barrier height of nickel silicide contacts formed on
Si1−xCx epitaxial layers”, IEEE Electron Devices Lett., vol.30, pp. 1320-1322, 2009.
[3.18] J.M. Larson et al., “Overview and status of metal S/D Schottky-barrier MOSFET Technology”, IEEE Electron Device Lett., vol.53, pp.1048-1058, 2006.
[3.19] W.J. Lee et al., “Work function variation of nickel silicide using an ytterbium buffer layer for Schottky barrier metal-oxide-semiconductor field-effect transistors”, J. Appl. Phys., vol.101, 103710, 2007.
[3.20] M. Sinha et al., “Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation, Appl. Phys. Lett., vol.92, 222114, 2008.
[3.21] R.T.P. Lee et al., “Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with
ultra-narrow Fin widths”, IEEE Electron Device Letter, vol.29, pp.382-385, 2008.
[3.22] A.T.Y. Koh et al., “Nickel-aluminum alloy silicides with high aluminum content for contact resistance reduction and integration in n-Channel field-effect transistors”, J. Electrochem. Soc., vol.155, H151-H155, 2008.
[3.23] S.W. Lee et al., “Ni silicide formation on epitaxial Si1−yCy/(001) layers, Thin Solid Films, vol.518, pp.7394-7397, 2010.
[3.24] L.J. Chen et al., “In situ TEM investigation of dynamical changes of nanostructures”, Mater. Sci. Eng., vol.70, pp.303-319, 2010.
[3.25] K.W. Richter et al., “NiAi1.74Si0.26 and NiSi1.83Ga0.17: Two materials with perfect lattice match to Si”, Applied Physics Lett., vol.83, pp. 497-499, 2003.
[3.26] R.T.P. Lee et al., “Novel nickel-alloy silicides for source/drain contact resistance reduction in n-channel multiple-gate transistors with sub-35nm gate length, Tech. Dig. - Int. Electron Devices Meeting, pp.851-854.
[3.27] A. Mogilatenko et al., Journal of Applied Physics, vol.111, pp.103~105, 2012.
[3.28] K. Tsutsui et al., Microelectron. Engineering, vol.85, pp.2000–2004, 2008.
[3.29] F. Allenstein et al., Microelectron. Eng., vol.82, pp.474–478, 2005.
Chapter 4 Ni(Ti) silicide formation on pre-amorphous implanted Si (001)
[4.1] R.W. Mann et al., Journal of Electrochem. Soc., vol.141, pp.1347-1350, 1994.
[4.2] G.L. Miles et al., Thin Solid Films, vol.290, pp.469-472, 1996.
[4.3] A. Lauwers et al., Appl. Surf. Sci., vol.91. pp.12-18, 1995.
[4.4] J.A. Kittl et al., Microelectronic Engineering, vol.50, pp.87-101, 2000.
[4.5] M. Diale et al., Appl. Phys. Lett., vol.62, pp.943-945, 1993.
[4.6] E.G. Colgan et al., Material Science Engineering, R16, pp.43-96, 1996.
[4.7] C.J. Choi et al., J. Electrochem. Soc., vol. 154, pp.759-763, 2007.
[4.8] S.W. Lee et al., “C redistribution during Ni silicide formation on Si1-yCy epitaxial layers”, J. Electrochem. Soc., vol.157, pp.297-300, 2010.
[4.9] C. Boulord et al., “Electrical and structural characterization of electroless nickel–phosphorus contacts for silicon solar cell metallization semiconductor devices, materials, and processing”, J. Electrochem. Soc., vol.157, pp.742-745, 2010.
[4.10] X.P. Qu et al., “Thermal stability, phase and interface uniformity of Ni-silicide formed by Ni-Si solid-state reaction”, Thin Solid Films., vol.462, pp.146-150, 2004.
[4.11] J. Demeulemeester et al., “Pt redistribution during Ni(Pt) silicide formation”, Appl. Phys. Lett., vol.93, 261912, 2008.
[4.12] D. Lee et al., “The effects of Ta on the formation of Ni-silicide in Ni0.95xTax0.05/Si systems”, Mater. Sci. Eng., B. 114, pp.241-245, 2004.
[4.13] Y. Setiawan et al., “Effect of Ti alloying in nickel silicide formation”, Thin Solid Films., vol.504, pp.153-156, 2006.
[4.14] F. Allenstein et al., “Influence of Al on the growth of NiSi2 on Si(001)”, Microelectronic Engineering, vol.82, pp.474-478, 2005.
[4.15] K. Tsutsui et al., “Improvement of thermal stability of Ni silicide on N+-Si by direct deposition of group III element (Al, B) thin film at Ni/Si interface”, Microelectronic Engineering, vol.85, pp.2000-2004, 2008.
[4.16] J. Luo, Y.L. Jiang, G.P. Ru, B.Z. Li, P.K. Chu, Silicidation of Ni(Yb) film on Si(001), J. Electron. Mater., vol.37, pp.245-248, 2008.
[4.17] W. Huang et al., “The improvement of thermal stability of nickel silicide by adding a thin Zr interlayer”, Microelectron. Engineering, vol.83, pp.345-350, 2006.
[4.18] W. Huang et al., “Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi”, Microelectron. Eng., vol.84, pp.678-683, 2007.
[4.19] W. Huang et al., “Effect of erbium interlayer on nickel silicide formation on Si(100)”, Appl. Surf. Sci., vol.254, pp.2120-2123, 2008.
[4.20] A.S.W. Wong et al., “F-enhanced morphological and thermal stability of NiSi films on BF2+-implanted Si(001)”, Applied Physics Letter, vol.81, pp.5138-5140, 2002.
[4.21] P.S. Lee et al., “Improved NiSi salicide process using presilicide N2+ implant for MOSFETs”, IEEE Electron Device Letter, vol.21, pp.566-568, 2000.
[4.22] B.Y. Tsui et al., “Improvement of the thermal stability of NiSi by germanium ion implantation”, Journal of Electrochemistry Society, vol.157, pp.137-143, 2010.
[4.23] O. Nakatsuka et al., “Improvement in NiSi/Si contact properties with C-implantation”, Microelectronic Engineering, vol.82, pp.479-484, 2005.
[4.24] Z. Kuwano et al., Appl. Phys. Lett., vol.56, pp.440-442, 1990.
[4.25] R.W. Hoffman et al., Physics of Thin Films, Vol. 3, Academic Press, New York, pp.211, 1996.
[4.26] D. Mangelinck et al., Appl. Phys. Lett., vol.75, pp.1736-1738, 1999.
[4.27] L.J. Chen et al., Mater. Sci. Semicond. Process., vol.4, pp.237-240, 2001.
[4.28] C.J. Tsai et al., Thin Solid Film, vol.365, pp.72-76, 2000.
[4.29] C.J. Tsai et al., Thin Solid Film, vol.350, pp91-95, 1999.
[4.30] S.W. Lu et al., Appl. Phys. Lett., vol.49, pp.1770-1772, 1986.
[4.31] Y.N. Erokhin at al., Appl. Phys. Lett., vol.63, pp3173, 1993.
[4.32] U. Falke et al., Phys. Stat. Sol., vol. (a). 162, pp.615-621, 1997.
[4.33] C.D. Line, et al., “Low temperature formation of NiSi2 from evaporated Silicon”, Phys. Stat. Sol., (a). vol.81, pp.123-128, 1984.
[4.34] J. Lu et al., Electrochem. Solid-State Lett., vol.13, pp.360-362, 2010.
Chapter 5 Future Works
[5.1] Shi-Li Zhang, “Untrathin Ni1-xPtx films as electrical contact in CMOS devices, ECS Trans”, vol. 45, Issue 6, pp.15-22, 2012.
[5.2] K. De Keyser et al., “Phase formation and thermal strability of untrathin Nickel Silicide on Si”, Applied Physics, Letter 96. 173503, 2010.
[5.3] Y. Nishi et. al, “Silicide wok function tuning by alloy approaches", IEEE International Electrical Device Meeting, pp. 135, 2007.
[5.4] Z. Zhang et. al, “Interface Dipole Engineering by dopant segregation”, IEEE International Electrical Device Meeting, vol. 28, No.7, pp.565, 2007. |