將戴爾他電路模型應用於類比電路的製程變異及老化效應分析之研究

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阮貴曹(Nguyen Cao Qui) 查詢紙本館藏

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電機工程學系

論文名稱

將戴爾他電路模型應用於類比電路的製程變異及老化效應分析之研究
(On the Applications of Delta Circuit Model for the Analysis of Process Variation and Aging Effects in Analog Circuits)

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摘要(中)

隨著積體電路製程尺寸越來越小，製程變異和老化效應對類比電路的良率及可靠度的影響也越來越大，如果設計的初期就能把這些非理想效應考慮進去，就可以大幅降低重新設計所需的成本。在傳統以模擬為基礎的解決方案中，雖然可以達到較高的精準度，但模擬所需的時間和代價卻非常高昂。因此，我們提出了一種新的模擬分析方法，可以同時考慮製程變異和老化效應，並在維持高精準度的前提之下，將模擬所需的資源降至合理的範圍。

首先，我們使用一組改進過的戴爾他元件模型來進行電路模擬，由這些元件所組成的戴爾他電路模型，可以藉由動態步階控制的原理，自動提升暫態分析的模擬速度。為了進一步提高效率，本論文提出了一種叢集式戴爾他QMC模擬技術，有效結合了戴爾他電路模型以及QMC取樣，以減少每個樣本的增量變化。由實驗結果可知，我們提出的方法可以將模擬速度提高兩個數量級，並具有幾乎相同的準確度，明顯的提高了良率分析的效率。

其次，本論文利用戴爾他模型為基礎，提出了一種漸進式的模擬技術，可以加快電路老化的模擬速度，並保有其原本的精準度，因為電路老化通常是一個緩慢變化的過程，我們提出的漸進式方法可以有效降低模擬的時間。而且，因為在蒙地卡羅的良率分析中，每一個樣本基本上都是相同的電路，只是參數有一些微小的差異，因此，對於效能衰退後的電路，我們也可以用漸進式的技術有效降低良率分析的時間。再加上我們提出的動態老化取樣技術，可以讓整體的模擬速度在最大估計誤差為1%時加速近五十倍，並且幾乎沒有損失精準度，有效地提升電路壽命分析的效率。

摘要(英)

As devices continue to shrink, the process variation and aging effects have increasing impacts on the circuit yield and reliability, particularly for analog circuits. If those non-ideal effects can be considered in early design stages, the re-design and re-spin costs can be significantly reduced. Traditional simulation-based methods to deal with the problems can achieve a high accuracy, but the simulation cost is very expensive. Thus, a new simulation-based analysis method that considers the process variation and aging effects is proposed, which can keep the cost at a reasonable scale while maintaining high accuracy.

First, the delta circuit model is improved with a set of basic delta devices for circuit simulation. By using the delta circuit model, simulation speed can be improved automatically due to the dynamic step control in transient analysis. In order to further improve the efficiency while combining the delta circuit model and QMC sampling, a cluster-based delta-QMC technique is proposed in this dissertation to reduce the delta change in each sample. Experimental results indicate that the proposed approach can increase simulation speed by two orders of magnitude with almost the same accuracy, which significantly improves the efficiency of yield analysis.

Second, an incremental simulation technique based on delta model is proposed to improve the simulation speed of lifetime yield analysis while maintaining the analysis accuracy. Because aging is often a gradual process, the proposed incremental technique is effective for reducing the simulation time. For yield analysis with degraded performance, this incremental technique also reduces the simulation time because each sample is the same circuit with small parameter changes in the Monte Carlo analysis. When the proposed dynamic aging sampling technique is employed, 50X speedup can be obtained with maximum estimation error of 1%, which considerably improves the efficiency of lifetime yield analysis.

關鍵字(中)

★ 三角洲电路模型

關鍵字(英)

★ delta circuit model
★ lifetime yield reliability analysis
★ variation analysis
★ Monte Carlo Simulation
★ QMC
★ Yield Analysis

論文目次

摘要 i
Abstract ii
Acknowledgment iii
Table of Contents iv
List of Figure vii
List of Tables ix
Acronyms x
Notation Illustration xi
Chapter 1 Introduction 1
1.1 The Analog IC Design Flow 1
1.2 Computer-Aided Design Tools for Analog Design 3
1.2.1 Circuit Simulation 6
1.2.2 Behavior Models 6
1.2.3 Topology Selection 7
1.2.4 Device Sizing 8
1.2.5 Layout Implementation 9
1.3 Process Variation and Reliability Issues 9
1.3.1 Process Variations 11
1.3.2 Aging Effects 14
1.4 Motivation 18
1.5 Organization 20
Chapter 2 Delta Devices and Delta Circuits 21
2.1 Signal Speed and Simulation Time 21
2.2 Linear Delta Devices 22
2.2.1 Delta Resistor 24
2.2.2 Delta capacitor and delta inductor 24
2.3 Previous Delta Models for Nonlinear Devices 25
2.4 Proposed Delta Models for Nonlinear Devices 26
2.4.1 Delta Dependent Sources 26
2.4.2 Delta Nonlinear Resistor, Capacitor and Inductor 27
2.4.3 Delta Diode 28
2.4.4 Delta MOSFET 29
2.5 Proposed Approach to Construct a Delta Circuit 30
2.6 Experimental Results 32
2.6.1 Experimental Setup 32
2.6.2 Results of the Inverter 32
2.6.3 Results of Second-Order Low-Pass Filter 34
2.7 Summary 37
Chapter 3 Cluster-Based Delta-QMC Technique for Yield Analysis 38
3.1 Background 38
3.1.1 Yield and Loss 38
3.1.2 Monte Carlo Method 38
3.1.3 Quasi Monte Carlo Method 39
3.1.4 Sobol points 40
3.1.5 Variance of QMC Method 41
3.2 Delta-QMC Techniques for MC Analysis 42
3.2.1 Delta-QMC simulation 42
3.2.2 Cluster-based delta-QMC Simulation 44
3.3 Experimental Results 49
3.3.1 Experimental Setup 49
3.3.2 Results of The Bandgap Reference 49
3.3.3 Results of The 64-bit SRAM 52
3.4 Summary 54
Chapter 4 Incremental Lifetime Yield Analysis Based on Delta Model 54
4.1 Transistor Aging Effects 54
4.2 Reviews of Reliability Simulators 57
4.1.1 Berkeley Reliability Tool (BERT) 57
4.1.2 RelXpert 58
4.1.3 Eldo Aging Simulator 59
4.3 The Related Works of Lifetime Yield Analysis 60
4.4 Incremental Lifetime Yield Analysis 62
4.4.1 Proposed Lifetime Yield Analysis Flow 63
4.4.2 Dynamic Aging Sampling 65
4.4.3 MC Simulations with Delta Circuit Models 66
4.5 Experimental Results 68
4.5.1 Experimental Setup 68
4.5.2 Results of Two-Stage NMOS Amplifier 69
4.5.3 Results of The Bandgap Reference 71
4.6 Summary 72
Chapter 5 Conclusions and Future Works 74
Reference 76
Publication List 87

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指導教授

劉建男(Chien-Nan Liu)

審核日期

2017-12-21

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