使用三五族以及矽基製程實現之高速高線性度高解析度追蹤保持放大器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：58

、訪客IP：3.142.124.83

姓名

林俞安(Yu-An Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用三五族以及矽基製程實現之高速高線性度高解析度追蹤保持放大器
(Design and Analysis of High Speed High Linearity High Resolutoin Track-and-Hold Amplifier in III-V andSilicon-Based Processes)

相關論文

★ 微波及毫米波切換器及四相位壓控振盪器整合除三除頻器之研製	★ 微波低相位雜訊壓控振盪器之研製
★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統	★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
★ 微波及毫米波行進波切換器之研製	★ 寬頻低功耗金氧半場效電晶體射頻環狀電阻性混頻器
★ 微波與毫米波相位陣列收發積體電路之研製	★ 24 GHz汽車防撞雷達收發積體電路之研製
★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究	★ 高功率高效率放大器與振盪器研製
★ 微波與毫米波寬頻主動式降頻器	★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
★ 寬頻主動式半循環器與平衡器研製	★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
★ 銻化物異質接面場效電晶體之研製及其微波切換器應用	★ 微波毫米波寬頻振盪器與鎖相迴路之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文主要探討應用於高速資料轉換系統微波及毫米波頻段高線性度追蹤與保持放大器，所提出的設計、研究以及理論計算分析結果將以實驗結果來做驗證。高速追蹤保持放大器的詳細介紹與設計考量將在第二章呈現。
第三章為使用砷化鎵增強型高速電子遷移率電晶體製程所實現之具有直流到82.4 GHz的寬頻放大器，所提出的寬頻放大器使用共源級架構搭配頻寬提升技術來做設計，其頻率響應、輸入阻抗以及輸出阻抗將加以分析以獲得最佳的設計方法，所提出的寬頻放大器架構具有328 GHz增益頻寬乘積和0.7 × 1毫米平方的電路面積，此放大器使用資料量為40 Gbps偽隨機二進位數列量測方式來驗證所提出的設計方法，所提出的寬頻放大器架構由於其良好的電路特性，適合應用在高資料傳遞系統中。
第四章為使用0.18微米矽鍺製程所實現的高速寬頻高線性的追蹤保持放大器，所提出的放大器使用開關射級隨偶器追蹤保持電路與疊接架構實現高解析度類比數位轉換，並且修改傳統的達靈頓寬頻電路，搭配電感提升技術以大幅提升整體的輸入頻寬，所提出的追蹤保持放大器架構具有94.3毫瓦特直流功耗、直流到27 GHz 3-dB輸入頻寬、45 dBc無失真動態範圍、-43.9 dB的總諧波失真，由於所提出的電路具有良好的電路特性，在使用多相位的時脈取樣下，將可實現超高速取樣速率。
第五章為使用砷化鎵增強型高速電子遷移率電晶體所實現的追蹤保持放大器，根據文獻，此電路為第一個使用砷化鎵增強型高速電子遷移率電晶體所設計的追蹤保持放大器，所提出的架構修改傳統開關源級隨偶器追蹤保持電路以增加整體電路的取樣率以及解析度，並且大幅減小開關時脈所造成的動態非線性度，搭配使用差動架構，輸出偶模非線性失真可大幅度的下降，追蹤保持放大器的無失真動態範圍以及總諧波失真亦可大幅度的下降，輸入以及輸出緩衝級使用分佈式放大器以及源級隨偶器架構去實現高輸入與輸出反射損耗，所提出的追蹤保持放大器架構具有直流到16 GHz的頻寬、46 dBc的無失真動態範圍以及13.5 GS/s取樣率。
第六章使用40奈米互補式金屬氧化物半導體電晶體製程實現高速以及高動態範圍的追蹤保持放大器，此電路使用差動消除器來做設計，實現接近無限大的保持模態隔離度，使用差動消除器架構亦改善了整體電路的線性度以及保持模態改變率，當輸入50 GS/s取樣率和5 GHz輸入信號時，模擬無失真動態範圍以及總諧波失真可分別達到47 dBc以及−44.6 dBc，所提出的追蹤保持放大器架構實現了60 GHz的輸入頻寬以及396 毫瓦特的直流功耗，此電路的量測結果和重新模擬結果將搭配電路布局電路技巧來做詳細的分析，由於此電路的高速、高線性度以及低直流功號的電路特性，所提出的追蹤保持放大器架構將可拿來與其他使用先進製程所設計的電路比較。
最後，總結了本論文所提出電路設計架構，並且提出未來設計方向以達到更高速、更寬頻、更好的電路線性度。

摘要(英)

Several microwave and millimeter wave (MMW) high linearity track-and-hold amplifiers (THAs) for high speed data conversion systems are presented in this dissertation. Design, investigation and analysis of THAs shown in this dissertation are verified by the experimental results. The introduction and design considerations of THA are demonstrated in Chapter 2 in details.
A compact DC-to-82.4-GHz broadband amplifier using 0.15 μm　GaAs E-mode PHEMT process is demonstrated in Chapter 3. The amplifier is implemented in common-source (CS) configuration with bandwidth extension technique. The frequency response and input and output impedances of the amplifier are investigated to obtain the design methodology. The amplifier exhibits a high gain-bandwidth product (GBP) of 328 GHz with a chip size of 0.7 × 1 mm2. Moreover, the amplifier is evaluated using pseudorandom bit stream (PRBS) signal with a data rate up to 40 Gbps. The proposed amplifier has potential for the high-speed data rate transmission due to its superior performance.
A broadband high-speed high-linearity THA is presented in Chapter 4 using 0.18 μm SiGe process. A switched emitter follower (SEF) track-and-hold (T/H) stage with cascode stage is adopted to achieve high resolution for analog-to-digital conversion. A modified Darlington amplifier with peaking technique is used to enhance the input bandwidth. With a DC power consumption of 94.3 mW, the proposed THA demonstrates a 3-dB input bandwidth from DC to 27 GHz, a maximum spurious-free dynamic range (SFDR) of 45 dBc, and a minimum total harmonic distortion (THD) of -43.9 dBc. The proposed circuit has potential for high-speed sampling rate as using time-interleaved architecture due to its superior performance.
Chapter 5 presents the design and analysis of the first GaAs-based THA. The conventional switched source follower (SSF) T/H stage is modified to enhance the sampling rate and resolution. The modified SSF T/H stage is designed and investigated to further reduce input-dependent timing jitter existed in the conventional SSF. Moreover, by using the differential topology, the even mode harmonic distortion is successfully suppressed and the SFDR and THD are improved. With the distributed amplifier (DA)-base input buffer and source follower-based output buffer, the proposed THA features a bandwidth from DC to 16 GHz, a maximum SFDR of 46 dBc and a maximum sampling rate of 13.5 GS/s.
In Chapter 6, a 40 nm CMOS high speed high dynamic range THA is proposed using a differential feed-through cancellation technique. The simulated isolation is approximate to infinity over the input bandwidth as the THA is operated in the hold mode. The linearity and droop rate are enhanced due to the feed-through cancellation. With a sampling rate of 50 GS/s and an input frequency of 5 GHz, the SFDR and THD are better than 47.6 dBc and −44 dBc, respectively. The simulated input bandwidth is up to 60 GHz, and the total DC power consumption is 396 mW. The measured results and resimulated results with several significant layout considerations are detailed as well. The proposed THA can be suitable for the handheld electronic applications, and the circuit performance can be compared to the advanced silicon-based THAs due to its high speed, good linearity, and low DC power.
Lastly, the future work and the conclusions are addressed in Chapter 7.

關鍵字(中)

★ 追蹤保持放大器
★ 毫米波積體電路
★ 混合訊號積體電路

關鍵字(英)

★ Track-an-Hold Amplifier
★ Microwave Integrated Circuit
★ Mixed-signal Integrated Circuit

論文目次

摘要.................................................................................................................................I
Abstract ........................................................................................................................III
致謝 ...............................................................................................................................V
Contents ....................................................................................................................VIII
List of Figures XII
List of Tables XIX
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Literatures Survey 4
1.3 Contributions 8
1.4 Dissertation Organization 10
Chapter 2 Introduction of THA 12
2.1 Introduction 12
2.2 Specifications Discussion 16
2.2.1 Linearity 16
2.2.2 Operated Speed 20
2.2.3 Resolution 24
2.2.4 Dynamic Range 28
2.2.5 DC Power Consumption 28
2.2.6 Chip Area 29
2.3 General Topologies of T/H Stage 30
2.3.1 Switched Capacitor (SC) 30
2.3.2 Switched Source Follower (SSF) / Switched Emitter Follower (SEF) 32
2.3.3 Diode switch 33
2.4 Measurement Setup 35
Chapter 3 A DC-to-82.4-GHz Broadband Amplifier Using Bandwidth Extension Technique in 0.15 μm PHEMT Process 37
3.1 Introduction of GaAs Process 38
3.2 Introduction of Low Pass Response 39
3.3 Performance Metrics 41
3.3.1 Gain-Bandwidth Product 41
3.3.2 Return Loss 42
3.3.3 1-dB Compression Point 43
3.3.4 Third-Order Intercept Point 44
3.3.5 Noise Figure 45
3.3.6 DC Power Consumption 46
3.3.7 Circuit Area 47
3.4 Conventional Broadband Amplifier 48
3.4.1 Peaking Technique 48
3.4.2 Darlington Pair 52
3.4.3 Distributed Technique 53
3.5 Analysis of Negative Feedback 57
3.6 Experimental Results 64
3.6.1 On-Wafer Measurement 64
3.6.2 Summary 71
3.7 Conclusion 73
Chapter 4 A 27-GHz 45-dBc SFDR Track-and-Hold Amplifier using Modified Darlington Amplifier and Casoded SEF in 0.18 μm SiGe Process 74
4.1 Introduction of SiGe BiCMOS Process 75
4.2 Cascoded Switched Emitter Follower Track-and-Hold Stage 76
4.3 Modified Darlington-Based Input Buffer 82
4.4 Source Follower Output Buffer 84
4.5 The Modified Darlington and Cascoded SEF T/H Stage THA 86
4.6 Experimental Results 89
4.7 Conclusion 92
Chapter 5 Design of Low Distortion Track-and-Hold Amplifier Using Dynamic Nonlinearity Degradation Topology in 0.15 μm GaAs Process...............93
5.1 Modified Switched Source Follower Track-and-Hold Stage 94
5.2 Distributed Amplifier-Based Input Buffer 99
5.3 The DA-Based Input Buffer and Modified SSF T/H Stage THA 101
5.4 Experimental Results 103
5.5 Conclusion 106
Chapter 6 A 60-GHz Bandwidth 50-GS/s Track-and-Hold Amplifier in 40 nm CMOS Process using Differential Cancellation Technique..................................107
6.1 Modified Switched Capacitor Track-and-Hold Stage 108
6.2 Active Inductive Peaking-Based Input & Output Buffers 114
6.3 The Modified SC T/H Stage and CS Amplifier Buffers THA 117
6.4 Simulated Results 119
6.5 Measured and Resimulated Results 122
6.5.1 Measured Results 122
6.5.2 Analysis of Layout Considerations 125
6.5.3 Performance Summary 126
6.6 Conclusion 127
Chapter 7 Conclution and Future Work....................................................................128
Reference 131
Publication List 137

參考文獻

[1] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K. Philips, and H. d. Groot, “A 46 μW 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset calibration,” in IEEE Journal of Solid-State Circuits, Vol. 52, No. 2, pp. 423-432, Feb. 2017.
[2] M. Krämer, E. Janssen, K. Doris, and B. Murmann, “A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 64, No. 2, pp. 116-120, Feb. 2017.
[3] C.-C. Liu, M.-C. Huang, and Y.-H. Tu, “A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC,” in IEEE Journal of Solid-State Circuits, Vol. 51, No. 12, pp. 2941-2950, Dec. 2016.
[4] Y. Lim, and M. P. Flynn, “A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 10, pp. 2331-2341, Oct. 2015.
[5] R. Sehgal, F. v. d. Goes, and K. Bult, “A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 7, pp. 1592-1603, Jul. 2015.
[6] J. Lin, D. Paik, S. Lee, M. Miyahara, and A. Matsuzawa, “An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 6, pp. 1399-1411, Jun. 2015.
[7] G. Tretter, M. M. Khafaji, D. Fritsche, C. Carta, and F. Ellinger, “Design and Characterization of a 3-bit 24-GS/s FlashADC in 28-nm Low-Power Digital CMOS,” in IEEE Transactions on Microwave Theory and Technique, Vol. 64, No. 4, pp. 1143-1152, Apr., 2016.
[8] Y. Xu, L. Belostotski, and J. W. Haslett, “A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 11, pp. 2316-2325, Nov. 2014.
[9] P. Ritter, S. L. Tual, B. Allard, and M. Möller, “Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold,” in IEEE Journal of Solid-State Circuits, Vol. 49, No. 9, pp. 1886-1894, Sep. 2014.
[10] B. V. Hieu, S. Beak, S. Choi, J. Seon, and T. T. Jeong, “Thermometer-to-binary Encoder with Bubble Error Correction (BEC) Circuit for Flash Analog-to-Digital Converter (FADC),” in IEEE International Conference on Communications and Electronics, pp. 102-106, Nha Trang, Vietnam, Aug. 2010.
[11] Y.-J. Chuang, H.-H. Ou, and B.-D. Liu, “A Novel Bubble Tolerant Thermometer-to-Binary Encoder for Flash A/D Converter,” in IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), pp. 315-318, Hsinchu, Taiwan, Apr. 2005.
[12] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, “Fat Tree Encoder Design for Ultra-High Seed Flash A/D Convertors,” in IEEE the 45th Midwest Symposium on Circuits and Systems (MWSCAS), Vol. 2, pp. II-87-II-90, Tulsa, Oklahoma, Aug. 2002.
[13] B. Xu, Y. Zhou, and Y. Chiu, “A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS,” in IEEE Journal of Solid-State Circuits, Vol. PP, No. 99, pp. 1-10, Jan. 2017.
[14] B. T. Reyes, R. M. Sanchez, A. L. Pola, and M. R. Hueda, “Design and Experimental Evaluation of a TimeInterleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems,” in IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. PP, No. 99, pp. 1-12, Dec. 2016.
[15] C.-Y. Lin and T.-C. Lee, “A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique,” in IEEE Journal of Solid-State Circuits, Vol. 63, No. 7, pp. 929-938, Jun. 2016.
[16] H. Orser, and A. Gopinath, “A 20 GS/s 1.2 V 0.13 μm CMOS Switched Cascode Track-and-Hold Amplifier,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 7, pp. 512-516, Jul., 2010.
[17] S. Yamanaka, K. Sano, and K. Murata, “A 20-Gs/s Track-and-Hold Amplifier in InP HBT Technology,” in IEEE Transactions on Microwave Theory and Technique, Vol. 58, No. 9, pp. 2334-2339, Sep., 2010.
[18] H.-G. Wei, U-F. Chio, Y. Zhu, S.-W. Sin, S.-P. U, and R. P. Martins, “A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 1, pp. 16-20, Jan., 2010.
[19] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 40 Gsamples/s InP-DHBT Track-&-Hold Amplifier,” in IEEE The 5th European Microwave Integrated Circuits Conference, pp. 61-64, Paris, France, Sep., 2010.
[20] Y. Borokhovych, J. C. Scheytt, “10 GS/s 8-bit bipolar THA in SiGe technology,” in IEEE NORCHIP, pp. 1-4, Lund, Sweden, Nov., 2011.
[21] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, M. Riet, J. Godin, and G. Pailler, “A 50-GHz small signal bandwidth 50 GSa/s Track&Hold Amplifier in InP DHBT technology,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, Montreal, Canada, Jun., 2012.
[22] H.-L. Chen, S.-C. Cheng, and B.-W. Chen, “A 5-GS/s 46-dBc SFDR Track and Hold Amplifier,” in IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPAC), pp. 636-639, New Taipei City, Taiwan, Nov., 2012.
[23] M. Macedo, G. W. Roberts, and I. Shih, “Track and hold for Giga-sample ADC applications using CMOS technology,” in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2725-2728, Seoul, South Korea, May, 2012.
[24] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, and J. Godin, “A 4 GSa/s, 16-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT technology,” in IEEE 20th Telecommunications Forum (TELFOR), pp. 502-505, Belgrade, Serbia, Nov., 2012.
[25] G. Tretter, D.Fritsche, C. Carta, and F. Ellinger, “10-GS/s Track and Hold Circuit in 28 nm CMOS,” in IEEE International Semiconductor Conference Dresden - Grenoble (ISCDG), pp. 1-3, Dresden, Germany, Sep., 2013.
[26] S. Daneshgar, Z. Griffith, M. Seo, and M. J. W. Rodwell, “Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers,” in IEEE Journal of Solid-State Circuits, Vol. 49, No. 10, pp. 2114-2126, Oct., 2014.
[27] S. Ma, L. Wang, H. Yu, and J. Ren, “A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS,” in IEEE Transactions on Microwave Theory and Technique, Vol. 62, No. 12, pp. 3500-3511, Dec., 2014
[28] H. Aggrawal, and A. Babakhani, “A 40GS/s Track-and-Hold Amplifier with 62dB SFDR3 In 45nm CMOS SOl,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, Tampa Bay, USA, Jun., 2014.
[29] D. Lal, M. Abbasi, and D. S. Ricketts, “A Compact, High Linearity 40GS/s Track-and-Hold Amplifier in 90nm SiGe Technology,” in IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, San Jose, USA, Sep, 2015.
[30] Y.-C. Liu, H.-Y. Chang, S.-Y. Huang, and K. Chen, “Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers,” in IEEE Transactions on Microwave Theory and Technique, Vol. 63, No. 9, pp. 2841-2853 Sep., 2015.
[31] K. N. Madsen, T. D. Gathman, S. Daneshgar, T. C. Oh, J. C. Li, and J. F. Buckwalter, “A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 11, pp. 2692-2702, Nov. 2015.
[32] Y.-A. Lin, Y.-C. Yeh, Y.-C. Liu, and H.-Y. Chang, “A 55-dB SFDR 16-GS/s track-and-hold amplifier in 0.18 μm SiGe using differential feedthrough cancellation technique,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-4, San Francisco, USA, May 2016.
[33] G. Tretter, D. Fritsche, M. Mahdi Khafaji, C. Carta, and F. Ellinger, “A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS,” in IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 63, No. 3, pp. 229-233, MAR. 2016.
[34] K. Vasilakopoulos, A. Cathelin, P. Chevaliert, T. Nguyen and S.P. Voinigescu, “A l08GS/s Track and Hold Amplifier with MOS-HBT Switch,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-4, San Francisco, USA, May 2016.
[35] A. Meyer, P. Desgreys, H. Petit, B. Louis, and R. Corbiere, “Single-ended/differential 2.5-GS/s Double Switching Track-and-Hold Amplifier with 26GHz Bandwidth in SiGe BiCMOS Technology,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, San Francisco, USA, May 2016.
[36] A. Moriyama, S. Taniyama, and T. Waho, “A Low-Distortion Switched-Source-Follower Track-and-Hold Circuit,” in IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 105-108, Seville, Spain, Dec. 2012.
[37] T. S. Mukherjee, D. C. Howard, J. D. Cressler, and K. T. Kornegay, “A wide Bandwidth SiGe Broadband Amplifier for 100 Gb/s Ethernet Applications,” in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1835-1838, Taipei, Taiwan, May. 2009.
[38] J. Kim, and J. F. Buckwalter, “Bandwidth Enhancement with Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier,” in IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 57, No. 8, pp. 1964-1972, Aug. 2010.
[39] T. Toifl, M. Kossel, C. Menolfi, T. Morf, and M. Schmatz, “A 23 GHz Differential Amplifier with Monolithically Integrated T-Coils in 0.09 μm CMOS Technology,” in IEEE MTT-S International Microwave Symposium (IMS), Vol. 1, pp. 239-242, Philadelphia, USA, Jun., 2003.
[40] C. Knochenhauer, B. Sedighi, and F. Ellinger, “A Comparative Analysis of Peaking Methods for Output Stages of Broadband Amplifiers,” in IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 58, No. 11, pp. 2581-2589, Nov. 2011.
[41] S.-H. Weng, H.-Y. Chang, C.-C. Chiong, and Y.-C. Wang, “Gain-Bandwidth Analysis of Broadband Darlington Amplifiers in HBT-HEMT Process,” in IEEE Transactions on Microwave Theory and Technique, Vol. 60, No. 11, pp. 3458-3473 Sep. 2012.
[42] P. V. Testa, G. Belfiore, R. Paulo, C. Carta, and F. Ellinger, “170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier,” in IEEE Journal of Solid-State Circuits, Vol. 50, No. 10, pp. 2228-2238, Oct. 2015.
[43] H.-Y. Chang, Y.-C. Liu, S.-H. Weng, C.-H. Lin, Y.-L. Yeh and Y.-C. Wang, “Design and analysis of a DC-43.5-GHz fully integrated distributed amplifier using GaAs HEMT-HBT cascode gain stage,” in IEEE Transactions on Microwave Theory and Technique, vol. 59, no. 2, pp.443-455, Feb. 2011.
[44] P. V. Testa, R. Paulo, C. Carta, and F. Ellinger, “250 GHz SiGe-BiCMOS Cascaded Single-Stage Distributed Amplifier,” in IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp.1-4, New Orleans, USA, Feb. 2011.
[45] T.-Y. Huang, Y.-H. Lin, J.-H. Cheng, J.-C. Kao, T.-W. Huang, and H. Wang, “A High-Gain Low-Noise Distributed Amplifier with Low DC Power in O.IS-l1m CMOS for Vital Sign Detection Radar,” in IEEE MTT-S International Microwave Symposium (IMS), pp. 1-3, Phoenix, USA, May, 2015.
[46] S. Daneshgar, Z. Griffith, and M. J. W. Rodwell, “A DC-100 GHz bandwidth and 20.5 dB gain limiting amplifier in 0.25 m InP DHBT technology,” in IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 1–4, Monterey, USA, Oct. 2013.
[47] B. Razavi, Principles of Data Conversion System Design, Willey-IEEE Press, 1994.
[48] G. Tretter, D. Fritsche, C. Carta and F. Ellinger, “Enhancing the Input Bandwidth of CMOS Track and Hold Amplifiers,” in IEEE 20th Microwaves, Radar, and Wireless Communication (MIKON), pp. 1-4, GDAŃSK, Poland, Jun. 2014.
[49] P. Wambacq and W. M. Sansen, Distortion Analysis of Analog Integrated Circuits. Boston, MA, USA: Kluwer Academic, 1998.
[50] P. G. Fonstad, Microelectronic Devices and Circuits. 2006 Electronic Edition.
[51] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuit, 2nd ed. Cambridge, UK. Cambridge University Press, 2004.
[52] B. Razavi, RF Microelectronics, Prentice Hall, 2011.
[53] P. V. Tesla, C. Carta, and F. Ellinger,“Analysis an Design of a 220-GHz Wideband SiGe BiCMOS Distributed Active Combiner,” in IEEE Transactions on Microwave Theory and Technique, vol. 64, no. 10, pp. 3049-3059, Oct. 2016.
[54] S.-H. Chen, “Dual-gate Device Modeling and Microwave/Millimeter-Wave Distributed Amplifier Design,” Master thesis, National Central University, Zhongli, Taoyuan, Taiwan, 2012.
[55] Sonnet User’s Guide, 12th ed. North Syracuse, NY: Sonnet Softw.Inc., 2009.
[56] Y. Li, W.-L. Goh and Y.-Z. Xiong, “A 2 to 92 GHz Distrubuted Amplifier Using 70-nm InP HEMTs,” in IEEE Wireless Symposium (IWS), Shenzhen, China pp.1-4, Mar. 2015.
[57] S.-H. Chen, C.-C. Shen, S.-H. Weng, Y.-C. Liu, H.-Y. Chang, and Y.-C. Wang, “Design of a DC-33 GHz cascode distributed amplifier using dual-gate device in 0.5-μm GaAs E/D-mode HEMT process,” in Asia-Pacific Microwave Conference, pp.728-730, Seoul, Korea, Nov. 2013.
[58] C. Shuicheng and W. Zhigong, “0-80GHz 0.15iImGaAs PHEMT Distributed Amplifier for Optic-Fiber Transmission Systems,” in Microwave and Millimeter Wave Technology, pp. 1–3, Guilin, China, April 2007.
[59] K.-Y. Lin, I-S. Chen, and H.-K. Chiou, “A 26 - 65 GHz GaAs pHEMT Cascaded Single Stage Distributed Amplifier with High Gain/Area Efficiency,” in Asia-Pacific Microwave Conference, pp. 722-725, Yokohama, Japan, Dec. 2006.
[60] K.-L. Deng, T.-W. Huang, and H. Wang, “Design and analysis of novel high-gain and broad-band GaAs PHEMT MMIC distributred amplifiers with traveling-wave gain stages,” IEEE Transaction on Microwave Theory and Technology, vol. 51, no. 11, pp. 2188-2196, Nov. 2003.
[61] K.-L. Deng, H. Wang, C. Glaser, and M. G. Stubbs, “A miniature high gain and broadband MMIC distributed amplifier,” in European Microwave Conference, vol. 2, pp. 615-618, Nuremburg, Germany, Oct. 2003.
[62] Gholamreza Nikandish and Ali Medi, “Design and Analysis of Broadband Darlington Amplifiers With Bandwidth Enhancement in GaAs pHEMT Technology,” IEEE Transaction on Microwave Theory and Technology, vol. 62, no. 8, pp. 1705–1715, Aug. 2012.
[63] F. Centurelli, P. Monsurro, and A. Trifiletti, “A model for the distortion due to switch on-resistance in sample-and-hold circuits,” in IEEE International Symposium on Circuits and System, pp. 21–24, Kos, Greece, May 2006.
[64] C.-L. Ler, A. K. b. A’ain, and A. V. Kordesch, “Compact, High-Q, and Low-Current Dissipation CMOS Differential Active Inductor”, IEEE Microwave and Wireless Component Letters, Vol. 18, No. 10, pp. 381-382, Oct. 2008.

指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2018-1-15

推文