應用於毫米波影像與太赫茲通訊之互補式金氧半94-GHz及200-GHz接收機設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：71

、訪客IP：18.191.222.143

姓名

謝宛庭(Wan-Ting Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於毫米波影像與太赫茲通訊之互補式金氧半94-GHz及200-GHz接收機設計
(94-GHz and 200-GHz CMOS Receiver Designs for Millimeter-Wave Imaging and THz Communication Applications)

相關論文

★ 以90-nm CMOS 製程實現之47-GHz 壓控振盪器設計	★ 應用於衛星通訊之QFN封裝X-/Ku-Band 低雜訊放大器設計
★ 使用電流路徑操作技術之無巴倫差動輸出倍頻器	★ 使用系統封裝技術實現高頻率射頻能量獵取電路
★ 擁有高增益之高模態介電共振器晶片上天線之340-GHz兆赫茲影像器	★ 以40-nm CMOS製程實現操作於100-GHz 之功率放大器設計
★ 應用於感測器與太赫茲通訊之互補式金氧半高頻電路設計	★ 應用於太赫茲成像系統340-GHz反射器天線系統和85-GHz二倍頻器
★ 使用40奈米互補式金氧半製程之85-GHz功率放大器設計	★ 應用於太赫茲通訊之 40 奈米互補式金氧半二倍頻器設計
★ 應用於太赫茲影像雷達及無線通訊系統之40-nm CMOS壓控振盪器

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本篇論文提出一個94-GHz接收機前端電路，採用90-nm CMOS製程，電路架構為整合五級之低雜訊放大器、寬頻之LO巴倫、單平衡架構之混頻器與倍頻器，其可在輸出10 MHz 之IF 頻率下提供量測轉換增益33 dB 與雙邊頻帶雜訊14 dB，在偏壓1 V 情況下只有20.4 mW之功耗。
為了驗證接收機前端電路、改善電路特性以及系統的完整性，本論文第二章提出94-GHz可調增益接收機電路，是採用90-nm CMOS製程整合GIPD製程實現，利用GIPD製程具有高阻值的矽基板，以及其低損耗金屬走線的優勢，為了節省成本與提升被動元件的Q值，GIPD製程適用於微波與毫米波被動電路的設計，封裝整合必是未來趨勢，本設計會驗證整合的連接結構。而RF端屬於94-GHz的高頻訊號，經過400 μm的線長再到達實際電路裡面，中間必有損耗是我們需要校正掉的，所以在GIPD會做de-embedding的動作。此可調增益接收機包括低雜訊放大器、倍頻器、混頻器和可調增益中頻放大器，主要為延續前一章的架構。校正後其量測結果在90 GHz有最大轉換增益48 dB，增益可調範圍為40 dB，RF的3-dB 頻寬為6.5 GHz，約為7.2%，IF的3-dB 頻寬在最高與最低增益分別為1 GHz和1.7 GHz，P1dB在最高與最低增益分別為-43.5 dBm和-29 dBm，雜訊指數則為12.5 dB以下，在偏壓1 V和1.2 V的情況下有共約62 mW之功耗。
隨著無線通訊系統的資料傳輸速率愈來愈快，本論文將設計太赫茲高速資料傳輸，提出創新之系統架構及電路，太赫茲高速收發機之200-GHz前端接收機之電路設計，利用40-nm CMOS技術實現，此電路架構為兩路的天線接收訊號，進入低雜訊放大器後當作混頻器RF輸入端，和藉由兩路100-GHz壓控震盪器產生訊號，且透過PLL去進行鎖定機制，將訊號穩定於100-GHz，再將訊號倍頻後，當作混頻器LO輸入端，而混頻器輸出端將同相的電流匯集至下一级的轉阻放大器再經限制放大器後輸出，此電路從低雜訊放大器輸入端到轉阻放大器的輸出端模擬有電壓轉換增益32 dB，P1dB為-23 dBm，輸出IF的3-dB頻寬約為13.4 GHz。

摘要(英)

In this thesis, a 94-GHz receiver front-end (RFE) in 90 nm CMOS technology is presented. The RFE integrates a five-stage low-noise amplifier, a broadband LO balun, a single-balanced mixer, and a doubler. The measurement system provides voltage conversion gain of 33 dB and double-sideband noise figure of 14 dB at the IF frequency of 10 MHz while only consuming 20.4 mW from a 1 V supply.
To verify the receiver front-end circuitry, improve circuit characteristics and system integrity, in chapter two, a 94-GHz receiver variable-gain in 90 nm CMOS integrated IPD process is presented. The CMOS chip is flipped and bonded onto the carrier through the transition. The advantages of IPD process are silicon substrate of high resistivity and low-loss metal to cut down the cost and improve the quality factor (Q) of passive components. However, we must verify the transition and calibrate the RF input loss of trace from GIPD to 90-nm interconnects by consideration of TRL de-embedding. The RX system which continuation of the previous chapter of the design include a five-stage low-noise amplifier, a broadband LO balun, a single-balanced mixer and a variable-gain amplifier. The measurement system provides voltage conversion gain of 48 dB, tuning range 40 dB at 86 GHz~92 GHz, IF bandwidth achieves 1.7 GHz at low gain and 1 GHz at high gain, the range of P1dB is -43.5 dBm ~ -29 dBm and double-sideband noise figure of 12.5 dB at the IF frequency of 10 MHz while iv consuming 62 mW from a 1 V and 1.2 V supply.
Finally, because of the wireless communication system popularity and the higher data rate. The third part is the design of the 200-GHz receiver using 40-nm CMOS technology. This circuit consists of antennas, VCOs, PLLs, LNAs, doublers, triplers, mixers, a TIA and a LA. The design of receiver is divided into two way from LNA to mixer and combine the in-phase current at mixer load to next stage, TIA. The simulated voltage gain from LNAs to TIA provide 32 dB, P1dB is -23 dBm and the IF bandwidth can achieve 13.4 GHz.

關鍵字(中)

★ 可調增益接收機
★ 接收機前端電路
★ 太赫茲高速資料傳輸
★ 低雜訊放大器
★ 倍頻器
★ 混頻器
★ 可調增益中頻放大器

關鍵字(英)

★ Gain-variable receiver
★ Receiver front-end
★ GIPD
★ de-embedding
★ RX system
★ LNA
★ Mixer
★ Doubler
★ VGA

論文目次

目錄
摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 IX
第一章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第二章 94-GHz 接收機前端電路 4
2.1　系統架構 4
2.2　94-GHz 接收機前端電路簡介 4
2.2.1 低雜訊放大器(LNA) 4
2.2.2 倍頻器(Doubler) 6
2.2.3 混頻器(Mixer) 8
2.3　94-GHz 接收機前端電路之佈局實現 10
2.4 94-GHz 接收機前端電路模擬與量測結果 13
2.4.1 量測考量與架設 13
2.4.2 接收機前端電路模擬結果 16
第三章 94-GHz可調增益接收機整合GIPD電路 21
3.1 系統架構 21
3.2 94-GHz可調增益接收機整合GIPD電路設計 22
3.2.1 低雜訊放大器(LNA) 22
3.2.2 可調增益放大器(VGA) 24
3.2.3 94-GHz 可調增益接收機電路整合GIPD之設計流程 29
3.3 系統封裝技術GIPD整合與佈局實現 29
3.4 94-GHz 接收機前端電路整合GIPD模擬與量測結果 34
3.4.1 量測考量與架設 34
3.4.2 94-GHz 可調增益接收機電路整合GIPD模擬與量測結果 39
第四章 200-GHz無線接收機電路 46
4.1 系統架構與介紹 46
4.2 200-GHz無線接收機電路設計 47
4.2.1 壓控振盪器(VCO) 47
4.2.2 低雜訊放大器(LNA) 52
4.2.3 倍頻器(Doubler) 55
4.2.4 混頻器(Mixer) 56
4.3 模擬結果與佈局考量 57
第五章結論與未來展望 61
5.1 總結 61
5.2 未來發展 61
參考文獻 62

參考文獻

[1] K. H. Chen, C. Lee and S. I. Liu, "A dual-band 61.4∼63GHz/75.5∼77.5GHz CMOS receiver in a 90nm technology," 2008 IEEE Symposium on VLSI Circuits, Honolulu, HI, 2008, pp. 160-161.
[2] B. Afshar, Y. Wang and A. M. Niknejad, "A Robust 24mW 60GHz Receiver in 90nm Standard CMOS," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, 2008, pp. 182-605.
[3] N. Zhang and K. O. Kenneth, "W-band pulsed radar receiver in low cost CMOS," IEEE Custom Integrated Circuits Conference 2010, San Jose, CA, 2010, pp. 1-4.
[4] J. Luo, L. Zhang, W. Zhu, L. Zhang, Y. Wang and Z. Yu, "A 64dB gain 60GHz receiver with 7.1dB noise figure for 802.11ad applications in 90nm CMOS," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 2401-2404.
[5] D. Lal, M. Abbasi and D. S. Ricketts, "A broadband, compact 140–170GHz double side-band receiver in 90nm SiGe technology," 2016 46th European Microwave Conference (EuMC), London, 2016, pp. 687-690.
[6] A. Tang, G. Virbila, D. Murphy, F. Hsiao, Y. Wang, Q. Gu, Z. Xu, Y. Wu, M. Zhu, and M.-C. F. Chang, “A 144 GHz 0.76 cm-resolution 14 sub-carrier SAR phase radar for 3-D imaging in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf., Feb. 2012, pp. 264–265.
[7] E. Ojefors, B. Heinemann, and U. R. Pfeiffer, “Subharmonic 220- and 320-GHz sige HBT receiver front-ends,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1397–1404, 2012.
[8] M. Elkhouly, M. Yanfie, S. Glisic, C. Meliani, F. Ellinger, J.C. Scheytt, "A 240 GHz direct conversion IQ receiver in 0.13 μm SiGe BiCMOS technology," IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp.305- 308, 2-4 June 2013
[9] S. V Thyagarajan et al, “A 240GHz wideband QPSK receiver in 65nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium, RFIC, pp. 357–360, 2014.
[10] N. Sarmah et al., “A Wideband Fully Integrtated SiGe Chipset for High Data Rate Communication at 240 GHz,” European Microwave Integrated Circuits Conference, 3-4 Oct 2016.
[11] P. R. Vazquez, J. Grzyb, N. Sarmah, B. Heinemann and U. R. Pfeiffer, "A 219–266 GHz fully-integrated direct-conversion IQ receiver module in a SiGe HBT technology," 2017 12th European Microwave Integrated Circuits Conference (EuMIC), Nuremberg, Germany, 2017, pp. 261-264.
[12] D. Fritsche, G. Tretter, P. Stärke, C. Carta and F. Ellinger, "A Low-Power SiGe BiCMOS 190-GHz Receiver With 47-dB Conversion Gain and 11-dB Noise Figure for Ultralarge-Bandwidth Applications," in IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 10, pp. 4002-4013, Oct. 2017.
[13] C. L. Ko, C. H. Li, C. N. Kuo, M. C. Kuo and D. C. Chang, "A 210-GHz Amplifier in 40-nm Digital CMOS Technology," in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 6, pp. 2438-2446, June 2013.
[14] Y. Wang, B. Afshar, L. Ye, V. C. Gaudet and A. M. Niknejad, "Design of a Low Power, Inductorless Wideband Variable-Gain Amplifier for High-Speed Receiver Systems," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 4, pp. 696-707, April 2012.
[15] Y. L. Yen, C. N. Kuo, C. F. Lee and K. Chen, "DC-to-5-GHz variable gain amplifier for high speed DSO," VLSI Design, Automation and Test(VLSI-DAT), Hsinchu, 2015, pp. 1-4.
[16] Peng, et al.,” A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan
Technique in 65 nm CMOS Technology,” IEEE J. Solid-State Circuits, vol.50, no.3, pp.
656-668, Mar. 2015.
[17] J. Lee, et al.,” A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS
Technology,”IEEE J. Solid-State Circuits, vol.45, no.12, pp. 2746-2756, Dec. 2010.
[18] Su, et al., “A 78-102 GHz Front-End Receiver in 90 nm CMOS Technology”, IEEE
Microw. Wireless Compon. Lett., vol. 21, no. 9, Sep. 2011.
[19] D. F. Williams et al., “Calibration for millimeter-wave silicon transistor characterization,”IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, pp. 658-668, Mar. 2014.
[20] H. Elwan, A. Tekin and K. Pedrotti, "A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2503-2514, Sept. 2009.
[21] H. Elwan, A. Tekin, K. Pedrotti and A. Emira, "A 49-dB continuous linear-in-dB IF VGA technique," 2009 IEEE International Symposium on Circuits and Systems, Taipei, 2009, pp. 2962-2965.
[22] J. Park, C. H. Lee, B. S. Kim and J. Laskar, "Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct-Conversion Receivers," in IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 12, pp. 4372-4380, Dec. 2006.
[23] Sarkas et al., "Silicon-Based radar and imaging sensors operationg above 120 GHz, "
IEEE MIKON , May. 2012.
[24]C. L. Ko, C. H. Li, C. N. Kuo, M. C. Kuo and D. C. Chang, "A 8-mW 77-GHz band CMOS LNA by using reduced simultaneous noise and impedance matching technique," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 2988-2991.
[25] Zhou, et al.,” A W-Band CMOS Receiver Chipset for Millimeter-Wave Radiometer Systems,” IEEE J. Solid-State Circuits, vol.46, no.2, Feb. 2011.

指導教授

李俊興(Chun-Hsing Li)

審核日期

2018-1-29

推文