以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：21

、訪客IP：3.149.252.8

姓名	涂祐豪(Yo-Hao Tu)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	應用於高速串列連結之關鍵技術設計與實現 (Design and Implementation of Key Technologies Applied to High-Speed Serial Links)
相關論文	★ 一種應用於觸控液晶顯示器的新型嵌入式開關 ★ 多重相位之延遲鎖定迴路倍頻器設計與分析 ★ 2.5Gbps串列收發器設計 ★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計 ★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路 ★ 全數位任意責任週期之同步映射延遲電路 ★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測 ★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統 ★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路 ★ 高解析度可變動責任週期之同步複製延遲電路 ★ 奈米CMOS晶片內序列傳輸之接收器 ★ 奈米CMOS晶片內序列傳輸之送器 ★ 基於鎖相迴路之多重相位脈波產生器 ★ 低能量時脈儲存元件之分析、設計與量測 ★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器 ★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	隨著積體電路製造技術促進高速數據傳輸的發展，資料傳輸量發展至每秒數兆位元(Gbps)。高速串列連結技術(High-Speed Serial Link Technology)是現今主要數據傳輸技術，亦被廣泛應用在有線收發裝置上，可以分為四個主要部分：發射端(TX)、接收端(RX)、傳輸通道(Channel)和時脈電路(CLK)。 　　發射端主要的功能為編碼，以確保資料的1和0的數量一致，並具有將資料串列化和功能模組化的用途。當資料傳輸速率已達每秒數兆位元，發射端的傳輸資料往往伴隨高次諧波，這將導致電磁干擾(Electromagnetic Interference, EMI)，並且嚴重影響周遭其他裝置。接收端主要的功能是等化，以確保接收到的資料和送出的資料一致，並具有將資料並列化和功能模組化的用途。隨著傳輸速率上升，訊號在傳輸通道中的損失越來越嚴重，加上傳輸通道的變異性，單一的補償機制已不敷使用，因此訊號完整性(Signal Integrity, SI)的考量也更顯得重要。晶片內外的雜訊來源，也是高速串列連結設計挑戰之一，包括有抖動，信號間的歪斜、電源和基體雜訊、其他線路產生的串擾以及設備本身的雜訊。因此，時脈電路也是必須要考慮周到的功能區塊。除此之外，為了使其具備更廣泛的應用性，拓展時脈電路的功能是一個重要議題。 　　於本論文中，對於發射端、接收端、傳輸通道和時脈電路的關鍵技術進行了討論和分析，並提出了相對應的電路以滿足其需求。透過提出具電磁干擾抑制技術之展頻時脈產生器(Spread-Spectrum Clock Generator, SSCG)及電源管理電路(Power Management In-tegrated Circuit, PMIC)，可降低電磁干擾帶來的影響。開發出具訊號完整性強化能力之連續時間線性等化器(Continuous Time Linear Equalizer, CTLE)和資料與時脈回復電路(Clock and Data Recovery, CDR)，可進一步提升接收端訊號的等化能力和可靠性。希望藉由抑制電磁干擾和訊號完整性強化技術，開發出適用於次世代的高速串列收發器，期盼其可具有低電磁干擾、高速資料傳輸功能及良好功率等效率表現。時脈電路中最常被採用的架構為鎖相迴路(Phase-Locked Loop, PLL)和延遲鎖定迴路(Delay-Lock Loop, DLL)，針對四個關鍵特性，分別是寬範圍(Wide-Range)技術、快速鎖定(Fast-Locking)技術、次諧波注入鎖定(Sub-Harmonically Injection-Locked)技術和非石英振盪器(Crystal-Less Clock Generator, CLCG)進行功能強化，希望透過這些技術使得時脈電路的功能可以更適用於高速的串列連結介面中。
摘要(英)	Advance in integrated circuit fabrication technology facilitates the high-speed transmission of data to be upward evolved into several gigabits per second (Gbps). The high-speed serial link (HSSL) technology is the major technique in modern data transmission. It is widely employed in wireline SerDes applications. The architecture of HSSL can be divided into four major parts, Transmitter (TX), Receiver (RX), Channel and Clock (CLK). 　The main work of the TX is the coding, to ensure that 1 and 0 are the same, in addition to the serialization and the modular. As the transmitted data rate has been upgraded into milti-Gbps, the signal of the data launched by the TX accompanies the higher order harmonics. It results in the power-radiated electromagnetic interference (EMI) issue and may stringently affect the other equipment in the vicinity. The main work of the RX is the equalization, to ensure that the received data is the same as transmitted data, in addition to the deserialization and the modular. The higher data transmission has the more channel loss. Furthermore, a simple compensation mechanism is not suitable for various transmission channels. Therefore, the signal integrity (SI) has to been considered carefully. On-chip and off-chip noise sources are also a challenge for the HSSL. They include the jitter, the inter-signal skew, the power supply and substrate noises, the crosstalk generated by other lines and the noise of the device itself. Therefore, the CLK is also the part have to be considerate well. Moreover, expanding the functionality of the clock circuit is an important issue to make it more widely applicable. 　In this dissertation, the key techniques of the four major parts, TX, RX, Channel and CLK, in HSSL are discussed and analyzed and corresponding circuit designs are presented to meet their needs, respectively. Through the introduction of a spread-spectrum clock generator and a power management integrated circuit with EMI suppression technology, the effects of EMI can be reduced. Through the introduction of a continuous time linear equalizer and a clock and data recovery with SI enhancement technology, the equalization ability and reliability of the signal on the RX side can further be improved. By the EMIsuppression and the SI enhancement technologies, the capabilities of low-EMI, high-speed data transmission and good power-efficient are derived for the next generation HSSL. The most common architectures of the clock generator are the phase-locked loop and delay-locked loop. To extend the functions of the four key features, which are the wide-range technique, the fast-locking technique, the sub-harmonically injection-locked technique and the crystal-less clock generator, it is expected that the functions of the clock generator can be more suitable for applications requiring an interface of the HSSL system.
關鍵字(中)	★ 高速串列連結 ★ 序列器/解除序列器 ★ 電磁脈衝干擾抑制 ★ 訊號完整性強化 ★ 時脈產生器 ★ 寬範圍 ★ 快速鎖定 ★ 次諧波式注入鎖定 ★ 非石英式時脈產生器	關鍵字(英)	★ High-Speed Serial Link ★ SerDes ★ Electromagnetic Interference Reduction ★ Signal Integrity Enhancement ★ Clock Generator ★ Wide-Range ★ Fast-Locking ★ Sub-Harmonically Injection-Locked ★ Crystal-Less Clock Generator
論文目次	摘要 i Abstract iii 誌謝 v Contents vii List of Figures xi List of Tables xviii Chapter 1 Introduction 1 1.1 Development of High-Speed Serial Link Technology 1 1.2 Architecture of High-Speed Serial Link Technology 2 1.2.1 Parallel Clock Serializer/Deserializer 2 1.2.2 Embedded Clock Serializer/Deserializer 3 1.2.3 8b/10b Serializer/Deserializer 4 1.2.4 Bit Interleaved Serializer/Deserializer 5 1.2.5 Summary 6 1.3 Application of High-Speed Serial Link Technology 7 1.4 Motivation 8 1.5 Dissertation Organization 10 Chapter 2 Critical Building Blocks in High-Speed Serial Link System 15 2.1 Transmitter in High-Speed Serial Link System 15 2.1.1 Fundamental of Transmitter Architecture 15 2.1.2 Electromagnetic Interference Reduction 16 2.2 Receiver in High-Speed Serial Link System 18 2.2.1 Fundamental of Receiver Architecture 18 2.2.2 Signal Integrity Enhancement 20 2.3 Channel Effect in High-Speed Serial Link System 23 2.3.1 Fundamental of Transmission-Line 23 2.3.2 Transmission-Line Model 24 2.3.3 Characteristic Impedance 26 2.3.4 Skin Effect 28 2.4 Clock Generator in High-Speed Serial Link System 32 2.4.1 Fundamental of Clock Generator 32 2.4.2 Overview of Wide-Range Technique 34 2.4.3 Overview of Fast-Locking Technique 36 2.4.4 Overview of Sub-Harmonically Injection-Locked Technique 40 2.4.5 Overview of Crystal-Less Clock Generator 44 Chapter 3 Electromagnetic Interference Reduction Techniques for High-Speed Serial Link 47 3.1 All-Digital Spread-Spectrum Clock Generator 47 3.1.1 Design Concept and Architecture Description 48 3.1.2 Circuit Implementation 56 3.1.3 Experimental Result 63 3.2 Low EMI DC-DC Buck Converter 66 3.2.1 Design Concept and Architecture Description 67 3.2.2 Circuit Implementation 81 3.2.3 Experimental Result 86 Chapter 4 Signal Integrity Techniques for High-Speed Serial Link 91 4.1 Power-Saving Adaptive Equalizer 91 4.1.1 Design Concept and Architecture Description 92 4.1.2 Circuit Implementation 103 4.1.3 Experimental Result 113 4.2 Clock and Data Recovery Circuit with Loop Gain Control 119 4.2.1 Design Concept and Architecture Description 119 4.2.2 Circuit Implementation 122 4.2.3 Experimental Result 127 Chapter 5 Key Techniques of Clock Generator 131 5.1 Wide-Range Delay-Locked Loop 132 5.1.1 Design Concept and Architecture Description 132 5.1.2 Circuit Implementation 144 5.1.3 Experimental Result 149 5.2 Wide-Range Phase-Locked Loop 152 5.2.1 Design Concept and Architecture Description 153 5.2.2 Circuit Implementation 158 5.2.3 Experimental Result 161 5.3 All-Digital Clock-Deskew Buffer 163 5.3.1 Design Concept and Architecture Description 163 5.3.2 Circuit Implementation 168 5.3.3 Experimental Result 171 5.4 Fast-Locking Phase-Locked Loop 174 5.4.1 Design Concept and Architecture Description 174 5.4.2 Circuit Implementation 176 5.4.3 Experimental Result 182 5.5 All-Digital Sub-Harmonically Injection-Locked Phase- Locked Loop 184 5.5.1 Design Concept and Architecture Description 185 5.5.2 Circuit Implementation 188 5.5.3 Experimental Result 191 5.6 All-Digital Crystal-Less Clock Generator 193 5.6.1 Design Concept and Architecture Description 193 5.6.2 Circuit Implementation 196 5.6.3 Experimental Result 203 Chapter 6 Conclusions and Future Works 207 6.1 Conclusions 207 6.2 Future Works 212 References 213 Publication List 224 Visiting and Honor 226 Chip Implementations 227
參考文獻	[1]D. Lewis, “SerDes architectures and applications,” in Proc. Euro DesignCon, 2004. [2]C.-L. Hung, “On techniques of clock generator used in high-speed wireline transmission systems,” Ph.D. dissertation, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2015. [3]K.-H. Cheng, C.-L. Hung, and C.-H. Chang, “A 0.77 ps RMS jitter 6-GHz spread-spectrum clock generator using a compensated phase-rotating technique” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1198–1213, May. 2011. [4]K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Int. Symp. Electromagn. Compat., Aug. 1994, pp. 227–231. [5]C.-H. Wong and T.-C. Lee, “A 6-GHz self-oscillating spread-spectrum clock generator,” IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 60, no.5, pp. 1264–1273, May 2013. [6]D sheng, C.-C. Chung, and C.-Y. Li, “A low-power and portable spread spectrum clock generator for SoC applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 6, pp. 1113–1117, Jun. 2011. [7]F. Pareschi, G. Setti, and R. Rovatti, “A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation,” IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 57, no. 10, pp. 2577–2587, Oct. 2010. [8]S.-T. Lin and S.-I. Liu, “A 1.5 GHz all-digital spread spectrum clock generator,” IEEE J. Solid-State Circuit, vol. 44, no. 11, pp. 3111–3119, Nov. 2009. [9]I-T. Lee, S.-H. Ku, and S.-I. Liu, “An all-digital spread-spectrum clock generator with self-calibrated bandwidth,” IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 60, no. 10, pp. 2813–2822, Nov. 2013. [10]M. Aoyama, K. Ogasawara, M. Sugawara, T. Ishibashi, T. Ishibashi, S. Shimoyama, K. Yamaguchi, T. Yanagita, and T. Noma, “3 Gbps, 5000 ppm spread spectrum serdes PHY with frequency tracking phase interpolators for serial ATA,” in Proc. IEEE Symp. On VLSI, Jun. 2003, pp. 107–110. [11]P.-J. Liu, J.-N. Tai, H.-S. Chen, J.-H. Chen, and Y.-J. E. Chen, “Spur-reduction design of frequency-hopping DC-DC converters,” IEEE Trans. Power Electron, vol. 27, no. 11, pp. 4763–4771, Nov. 2012. [12]S. K. Dunlap, and T. S. Fiez, “A noise-shaped switching power supply using a delta–sigma modulator,” IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 51, no. 6, pp. 1051–1061, Jun. 2004. [13]E. N. Y. Ho and P. K. T. Mok, “Design of PWM ramp signal in vltage-mode CCM random switching frequency buck converter for conductive EMI reduction,” IEEE Trans. Circuits Syst. I, Reg. Paper, vol. 60, no. 2, pp. 505–515, Feb. 2013. [14]J. N. Babanezhad, “A 3.3 V analog adaptive line-equalizer for fast Ethernet data com-munication,” in Proc. IEEE Custom Integr. Circuits Conf., May, 1998, pp. 343–346. [15]S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design, Hoboken, NJ, USA: Wiley, 2000. [16]B. Razavi, Design of Integrated Circuits for Optical Communications, New York, NY, USA: McGraw-Hill, 2003. [17]J. Hancock, “Identifying sources of jitter,” in Proc. Euro DesignCon, 2004. [18]J. T. Stonick, G. Y. Wei, J. L. Sonntag, and D. K. Weinlader, “An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS,” IEEE J. Solid-State Circuits, vol. 38, no.3, pp. 436–443, Mar. 2003. [19]T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J. Mason, W. Rhee, H. Ainspan, B. Parker, and M. Beakes, “A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633–2645, Dec. 2005. [20]B. Kim, J. F. Bulzacchelli and D. J. Friedman, “A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44 , no. 12 , pp. 3526–3538 , Dec. 2009. [21]S. Shahramian and A. C. Carusone, “A 0.41 pJ/Bit 10 Gb/s hybrid 2 IIR and 1 discrete-time DFE tap in 28 nm-LP CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1722–1735, Feb. 2015. [22]J. S. Choi, M. S. Hwang, and D. K. Jeong, “A 0.18-um CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 419–425, Mar. 2004. [23]G. Zhang and M. M. Green, “A 10 Gb/s BiCMOS adaptive cable equalizer,” IEEE J. Solid-State Circuits, vol. 40, no.11, pp. 2132–2140, Nov. 2005. [24]J. Lee, “A 20-Gb/s adaptive equalizer in 0.13-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058–2066, Sep. 2006. [25]S. Gondi and B. Razavi, “Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999–2011, Sep. 2007. [26]C.-F. Liao and S.-I. Liu, “A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2492–2502, Nov. 2008. [27]S.-I. Liu and C.-Y. Yang, Phase-Locked Loop, Taichung City, Taiwan (R.O.C.): Tsanghai, 2008. [28]W.-Y. Lee, K.-D. Hwang, and L.-S. Kim, “A 5.4/2.7/1.62-Gb/s receiver for DisplayPort version 1.2 with multi-rate operation scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2858–2866, Nov. 2012. [29]D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2713–2725, Dec. 2005. [30]J. Kim and D.-K. Jeong, “Multi-gigabit-rate clock and data recovery based on blind oversampling,” IEEE Commun. Mag., vol. 41, no. 12, pp. 68–74, Dec. 2003. [31]S.-W. Kwon, J.-Y. Lee, J. Lee, K. Han, T. Kim, S. Lee, J.-S. Lee, T. Yoon, H. Won, J. Park, and H.-M. Bae, “An automatic loop gain control algorithm for bang-bang CDRs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 12, pp. 2817–2828, Dec. 2015. [32]H. J. Jeon, R. Kulkarni, and Y. C. Lo, “A bang-bang clock and data recovery using mixed mode adaptive loop gain strategy,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1398–1415, Jun. 2013. [33]H. Song, D. S. Kim, D. H. Oh, S. Kim, and D. K. Jeong, “A1.0–4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and adaptive proportional gain control,” IEEE J. Solid-State Circuits, vol. 46, pp. 424–434, Feb. 2011. [34]J. Song, I. Jung, M. Song, Y. H. Kwak, S. Hwang, and C. Kim, “A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a with weighted phase and frequency detection,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 2, pp.268–278, Feb. 2013. [35]R.-J. Yang and S.-I. Liu, “A 40–550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 361–373, Feb. 2007. [36]C.-N. Chuang and S.-I. Liu, “A 0.5-5-GHz wide-range multiphase DLL with a calibrated charge pump,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 939–943, Nov. 2007. [37]C.C. Chen, and S.I. Liu, “An infinite phase shift delay-locked loop with voltage-controlled sawtooth delay line,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2413–2421, Nov. 2008. [38]X.Yu, W. Rhee, Z.Wang, J. B. Lee, and C. Kim, “A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation,” in IEEE Int. ISSCC Dig. Tech. Papers, Feb. 2009, pp. 398–400. [39]Y.-S. Kim, S.-K. Lee, H.-J. Park, and J.-Y. Sim, “A 110 MHz to 1.4 GHz locking 40-Phase all-digital DLL,” IEEE J. Solid-State Circuits, vol. 46, no.2, pp. 435–444, Feb. 2011. [40]K. H. Cheng, C. W. Su, M. J. Wu, and Y. L. Chang, “A wide-range DLL-based clock generator with phase error calibration,” in Proc. IEEE Int. Conference on Electron., Circuits and Syst., Aug. 2008, pp. 798–801. [41]S. Ok, K. Chung, J. Koo, and C. Kim, “An antiharmonic, programmable, DLL-based frequency multiplier for dynamic frequency scaling,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 7, pp. 1130–1134, Jul. 2010 [42]A. Ojani, B. Mesgarzadeh, and A. Alvandpour, “Modeling and analysis of harmonic spurs in DLL-based frequency synthesizers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.61, no. 11, pp. 3075–3084, Nov. 2014. [43]I-T. Lee, Y.-T. Tsai, and S.-I. Liu, “A wide-range PLL using self-healing prescaler VCO in 65-nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 2, pp. 250–258, Feb. 2013. [44]T. Ebuchi, Y. Komatsu, T. Okamoto, Y. Arima, Y. Yamada, K. Sogawa, K. Okamoto, T. Morie, T. Hirata, S. Dosho, and T. Yoshikawa, “A 125–1250 MHz process-independent adaptive bandwidth spread spectrum clock generator with digital controlled self-calibration,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 763–774, Mar. 2009. [45]C.-C. Chen, C.-C. Li, B.-J. Huang, K.-Y. Lin, and H. Wang, “Ring-based triple-push VCOs with wide continuous tuning ranges,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 9, pp. 217 3–2183, Sept. 2009. [46]O. Momeni and E. Afshari, “High power terahertz and millimeter-wave oscillator design a systematic approach,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 583–597, Mar. 2011. [47]T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, I. Yoshida, K. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, and T. Okuda, “A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1656–1668, Nov. 1996. [48]T. Seaeki, H. Nakamura, and J. Shimizu, “A 10 ps jitter 2 clock cycle lock time CMOS digital clock generator based on an interleaved synchronous mirror delay scheme,” in Proc. IEEE Symp. On VLSI, Jun. 1997, pp. 109–110. [49]K. Sung, B. D. Yang, and L. S. Kim, “Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme,” in Proc. IEEE Int. Symp. Circuits Syst., May 2002, pp. 671–674. [50]T. Saeli, K. Minami, H. Yoshida, and H. Suzuki, “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 372–379, Mar. 1999. [51]K. Sung and L. S. Kim, “A high-resolution synchronous mirror delay using successive approximation register,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1997–2004, Nov. 2004. [52]K.-H. Cheng, C.-W. Su, S.-W. Lu, “Wide-range synchronous mirror delay with arbitrary input duty cycle,” IET Electron. Lett., vol. 44, no.11, pp. 655–667, May 2008. [53]K.-H. Cheng, K.-W. Hong, C.-H. Chen, and J.-C. Liu, “A high precision fast locking arbitrary duty cycle clock synchronization circuit,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 7, pp. 1218–1228, Jul. 2011. [54]J.-B. Lan, F.-C. Lai, Z.-Q. Gao, H. Ma and J.-W. Zhang, “A nonlinear phase frequency detector for fast-lock phase-locked loops”, in Proc. Asian Solid-State Circuits Conf., Oct. 2009, pp. 1117–1120. [55]J.-C. Chih, C.-T. Chiu, J.-M. Wu, S.-H. Hsu, and Y.-S. Hsu, “Piecewise-linear phase frequency detector for fast-lock phase-locked loops,” in Proc. IEEE Int. Midwest Symp. on Circuits and Syst., Aug. 2011, pp. 1–4. [56]C.-S. Lin, T.-H. Chien, C.-L. Wey, C.-M. Huang, and Y.-Z. Juang, “An edge missing compensator for fast settling wide locking range phase-locked loops,” IEEE J. Solid-State Circuits, vol.44, no.11, pp.3102–3109, Nov. 2009. [57]W.-H. Chiu, Y.-H. Huang, T.-H. Lin, “A dynamic phase error compensation technique for fast-locking phase-locked loops,” IEEE J. Solid-State Circuits, vol.45, no.6, pp.1137–1148, Jun. 2010. [58]Y.-F. Lin, “A 2.5 GHz fast locking self-calibration phase-locked loop designed in 90 nm process,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2008. [59]J. Lee, and H.-D. Wang, “Study of subharmonically injection-locked PLLs,” IEEE J. Solid-State Circuit, vol. 44, no. 5, pp. 1539–1553, May 2009. [60]Y. H. Kao, Radio-Frequency Phase-Locked Loop Integrated Circuit Design, Taichung City, Taiwan (R.O.C.): Tsanghai, 2005. [61]S. Ye, L. Jansson, and I. Galton, “A multiple-crystal interface PLL with VCO realignment to reduce phase noise,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, Dec. 2002. [62]M. S. McCorquodale, J. D. O′ Day, S. M. Pernia, G. A. Carichner, S. Kubba, and R. B. Brown, "A monolithic and self-referenced RF LC clock generator compliant with USB 2.0," IEEE J. Solid-State Circuits, vol. 42, no.2, pp. 385–399, Feb. 2007. [63]M. S. McCorquodale, S. M. Pernia, J. D. O’Day, G. Carichner, E. Marsman, N. Nguyen, S. Kubba, S. Nguyen, J. Kuhn, and R. B. Brown, “A 0.5-to- 480MHz self-referenced CMOS clock generator with 90ppm total frequency error and spread-spectrum capability,” in IEEE Int. ISSCC Dig. Tech. Papers, Feb. 2008, pp. 350–351. [64]F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, “A low-voltage mobility-based frequency reference for crystal-less ULP radios,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2002–2009, July. 2009. [65]F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, “A 65-nm CMOS temperature-compensated mobility-based frequency reference for wireless sensor networks” , IEEE J. Solid-State Circuits, vol.46, no.7, pp.1544–1552, Jul. 2011. [66]Y. Lu, G. Yuan, L. Der, W.-H. Ki, and C. P. Yue, “A ±0.5 % precision on-chip frequency reference with programmable switch array for crystal-less applications” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 642–646, Oct. 2013. [67]Y.-H. Chiang, and S.-I. Liu, “A submicrowatts 1.1 MHz CMOS relaxation oscillator with temperature compensation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 12, pp. 837–841, Dec. 2013. [68]Y.-H. Chiang, and S.-I. Liu, “Nanopower CMOS relaxation oscillator with sub-100 ppm/°C temperature coefficient,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 9, pp. 661–665, Jun. 2014. [69]W.-H. Sung, S.-Y. Hsu, J.-Y. Yu, C.-Y. Yu, and C.-Y. Lee, “A frequency accuracy enhanced sub-10uW on-chip clock generator for energy efficient crystal-less wireless biotelemetry applications,” in Proc. IEEE Symp. On VLSI, Jun. 2010, pp. 115–116. [70]J.-C. Liu, W.-C. Lee, H.-Y. Huang, K.-H. Cheng, C.-J. Huang, Y.-W. Liang, J.-H. Peng, and Y.-H. Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in Proc. Asian Solid-State Circuits Conf., 2012, pp.117–120. [71]Y.-H. Huang, “A 6 GHz all-digital spread-spectrum clock generator with high speed phase selector,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2013. [72]H.-Y. Huang and F.-C. Tsai, ‘‘Analysis and optimization of ring oscillator using sub-feedback scheme,’’ in Proc. IEEE Int. Symp. Design and Diagnostics of Electron. Circuits and Syst., Apr. 2009, pp. 28–29. [73]V. Kratyuk, ‘‘Digital phase-locked loops for multi-gHz clock generation,” Ph.D. dissertation, Dept. Elect. and Comput. Eng., Oregon State Univ., Corvallis, OR, USA, 2006. [74]D. D. Caro, C. A. Romani, N. Petra, A. G. M. Strollo, and C. Parrella, “A 1.27 GHz all-Digital spread spectrum clock generator/synthesizer in 65 nm CMOS,” IEEE J. Solid-State Circuit, vol. 45, no. 5, pp. 1048–1060, Mar. 2010. [75]S. Jang, S. Kim, S.-H. Chu, G.-S. Jeong, Y. Kim, and D.-K. Jeong, “An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation,” in Proc. IEEE Symp. On VLSI, Jun. 2015, pp. C136–C137. [76]D. D. Caro, F. Tessitore, G. Vai, N. Imperato, N. Petra, E. Napoli, C. Parrella, and A. G. M. Strollo, “A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS,” IEEE J. Solid-State Circuit, vol. 45, no. 5, pp. 1048–1060, Mar. 2010. [77]H.-F. Ting, “A Low EMI DC-DC buck converter with multiple-slopes spread-spectrum clock technique,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2015. [78]H.-H. Ko, “A high efficiency synchronous CMOS switching buck regulator with accurate current sensing technique,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2007. [79]C.-H. Tsai, C.-H. Yang, and J.-C. Wu, “A digitally controlled switching regulator with reduced conductive EMI spectra” IEEE Trans. Ind. Electron, vol. 60, no. 9, pp. 3938–3947, Sep. 2013. [80]W.-R. Liou, M.-L. Yeh, P.-S. Chen, C.-C. Tseng, T.-Y. Huang, S.-C. Lin, C.-Y. Lin, and C.-H. Sun, “Monolithic low-EMI CMOS DC–DC boost converter for portable applications” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 2, pp. 420–424, Feb. 2014. [81]M.-J. Lee, “A low-power adaptive equalizer with closeable digital-control self-slope detection,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2015. [82]D. Lee, J. Han, G. Han, and S. M. Park, “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2861–2873, Dec. 2010. [83]M. Lee and A. A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. [84]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, no. 3, pp. 220–224, Mar. 2006. [85]K.-H. Cheng, J. C. Liu, C.-Y. Chang, S. Y. Jiang, and K. W. Hong, “Built-in jitter measurement circuit with calibration techniques for a 3-GHz clock generator,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 8, pp. 1325–1335, Aug. 2011. [86]H. Y. Huang, J. C. Liu, and K. H. Cheng, “All-digital PLL using pulse-based DCO,” in IEEE Int. Conf. on Electron., Circuits and Syst., Dec. 2007, pp. 1268–1271. [87]K. H. Cheng, Y. C. Tsai, Y. H. Wu, and Y. F. Lin, “A 5-Gb/s inductorless CMOS adaptive equalizer for PCI express generation II applications,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 57, no. 5, pp. 324–328, May 2010. [88]W.-S. Kim, C.-K. Seong, andW.-Y. Choi, “A 5.4-Gbit/s adaptive continuous-time linear equalizer using asynchronous undersampling histograms,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 9, pp.553–557, Sep. 2012. [89]H. Liu, Y. Wang, C. Xu, X. Chen, L. Lin, Y. Yu, W. Wang, A. Majumder, G. Chui, D. Brown, and A. Fang, “A 5-Gb/s serial-link redriver with adaptive equalizer and transmitter swing enhancement,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 61, no.4, pp. 1001–1011, Apr. 2014. [90]T.-T. Chen, “A clock and data recovery circuit with adaptive gain control,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2015. [91]M. Brownlee, P. K. Hanumolu, and U. K. Moon, “A 3.2 Gb/s oversampling CDR with improved jitter tolerance,” in Proc. IEEE Custom Integrated Circuits Conf., 2007, pp. 353–356. [92]W.Y. Lee and L.S. Kim, “A 5.4-Gb/s clock and data recovery circuit using seamless loop transition scheme with minimal phase noise degradation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 11, pp. 2518–2528, Nov. 2012. [93]Y.-H. Tu, “A wide range delay-locked loop with phase error calibration and frequency multiplier,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2010. [94]J.-R. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62–70, Feb. 1989. [95]J.-R. Yuan and C. Svensson, “Fast CMOS nonbinary divider and counter,” Electron. Lett., vol. 29, no. 13, pp. 1222–1223, Feb. 1993. [96]K.-H. Cheng, C.-W. Su, and K.-F. Chang, “A high linearity, fast-locking pulsewidth control loop with digitally programmable duty cycle correction for wide range operation,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 399–413, Feb. 2008. [97]J. S. Wang and C. Y. Cheng, “An all-digital delay-locked loop using an in-time phase maintenance scheme for low-jitter gigahertz operations,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 2, pp. 395–404, Feb. 2015. [98]J.-H. Lim, J.-H. Bae, J. Jang, H.-K. Jung, H. Lee, Y. Kim, B. Kim, J.-Y. Sim, and H.-J. Park, “A delay locked loop with a feedback edge combiner of duty-cycle corrector with a 20%–80% input duty cycle for SDRAMs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 2, pp. 141–145, Feb. 2016. [99]M. H. Hsieh, L.-H. Chen, S.-I. Liu, and C. C.-P. Chen, “A 6.7 MHz to 1.24 GHz 0.0318 mm2 fast-locking all-digital DLL using phase-tracing delay unit in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 412–427, Feb. 2016. [100]E. Bayram, A. F. Aref, M. Saeed, and R. Negra, “1.5–3.3 GHz, 0.0077 mm2, 7 mW all-digital delay-locked loop with dead-zone free phase detector in 0.13 μm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 1, pp. 39–50, Jan. 2018. [101]Y.-C. Hsu, “A wide range triple-push phase-locked loop with bandwidth calibration,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2016. [102]J. Kim, M. A. Horowitz, G.-Y. Wei, “Design of CMOS adaptive-bandwidth PLL/DLLs : A general approach,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, no. 11, pp. 860–869, Nov. 2003 [103]C.-H. Hsu, “A low supply voltage synchronous mirror delay with quadrature phase output,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2012. [104]M.-V. Krishna, M.-A. Do, K.-S. Yeo, C.-C. Boon, and W.-M. Lim, “Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 72–82, Jan. 2010. [105]M.-Y. Kim, D. Shin, H. Chae, C. Kim, “A low-jitter open-loop-all-digital clock generator with two-cycle lock-time,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 10, pp. 1461–1469, 2009. [106]Y.-G. Chen, H.-W. Tsao, and C.-S. Hwang, “A fast-locking all-digital deskew buffer with duty-cycle correction,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 270–280, Feb. 2013. [107]K.-H. Cheng, K.-W. Hong, C.-F. Hsu, and B.-Q. Jiang, “An all-digital clock synchronization buffer with one cycle dynamic synchronizing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1818–1827, Oct. 2012. [108]P.-Y. Li, “A fast-locking phase-locked loop with a digital band selector and an adaptive phase frequency detector,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2013. [109]T.-H. Lin and Y.-J. Lai, “An agile VCO frequency calibration technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 340–349, Feb. 2007. [110]J. Shin and H. Shin, “A 1.9–3.8 GHz fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 665–675, Mar. 2012. [111]B. Zhao, Y. Lian, and H. Yang, “A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 60, no. 5, pp. 1188–1199, May 2013. [112]L. Bertulessi, L. Grimaldi, D. Cherniak, C. Samori, and S. Levantino, “A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range,” in IEEE Int. ISSCC Dig. Tech. Papers, Feb. 2018, pp. 252–254. [113]W.-R. Wang, “A high division-ratio all-digital sub-harmonically injection-locked PLL with chaotic injection timing technique,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2015. [114]C.-Y. Chang, “A 0.5 V all digital crystal-less clock generator with temperature compensation,” M.S. thesis, Dept. Elect. Eng., National Central Univ., Taoyuan City, Taiwan (R.O.C.), 2015. [115]Y.-H. Tu, J.-C. Liu, K.-H. Cheng, H.-Y. Huang, C.-C. Hu, “A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC,” IEICE Electron. Express, vol.13, no. 2, pp. 1–12, Feb. 2016. [116]H.-Y. Huang, W.-C. Hung, H.-W. Cheng and C.-H. Lu, “All digital time-to-digital converter with high resolution and wide detect range,” Eng. Lett., vol.19, no. 3, pp. 261–264, Aug. 2011 [117]V. D. Smedt, P. D. Wit, W. Vereecken, and M. S. J. Steyaert, “A 66 uW 86ppm/°C ful-ly-integrated 6 MHz wienbridge oscillator with a 172 dB phase noise FOM,” IEEE J. Solid-State Circuits, vol.44, no. 7, pp. 1990–2001, Jul. 2009. [118]K. Tsubaki, T. Hirose, N. Kuroki, and M. Numa, “A 32.55-kHz, 472-nW, 120ppm/°C on chip, variation tolerant CMOS relaxation oscillator for a real-time clock application,” in Proc. IEEE European Solid-State Circuits Conf., Sep. 2013, pp. 315–318 [119]W.-H. Sung, S.-Y. Hsu, J.-Y. Yu, C.-Y. Yu, and C.-Y Lee, “A frequency accuracy enhanced sub-10μW on-chip clock generator for energy efficient crystal-less wireless biotelemetry application,” in Proc. IEEE Symp. On VLSI, Jun. 2010, pp. 115–116. [120]K. Choe, O. D. Bernal, D. Nuttman, and M. Je, “A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs,” in IEEE Int. ISSCC Dig. Tech. Papers, Feb. 2009, pp. 402–403. [121]Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, “An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage,” in IEEE Int. ISSCC Dig. Tech. Papers, Feb. 2009, pp. 404–405.
指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2018-5-10
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare