基於全頻譜分析與自動編碼器之EEG訊號特徵提取

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姓名

楊舜翰(Shun-Han Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於全頻譜分析與自動編碼器之EEG訊號特徵提取
(EEG Feature Extraction based on Holo-Hilbert Spectral Analysis and Autoencoder)

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摘要(中)

本論文討論新型的腦電圖(Electroencephalography, EEG)訊號特徵提取方式。EEG訊號是非線性非平穩訊號，相較於基於假設訊號為線性平穩的傅立葉轉換，希爾伯特-黃轉換(Hilbert Huang Transform, HHT)更適用於處理該類訊號，但該運算在實現上需花費較多時間，然而使用傳統方法的分析需先將資料透過感測器接收後傳輸至電腦再作特徵提取會花費較多的時間，且在傳輸大量資料也較為耗時，若能先經由韌體進行特徵提取降低資料維度或直接由韌體完成腦機介面則可大幅提升效率，本論文欲在韌體上以較少的資源達成腦電訊號及時解析，目標簡化運算流程及運算複雜度。
在本篇論文中，使用現場可程式邏輯閘陣列(Field-Programmable Gate Array, FPGA)實現透過本論文提出的演算法來進行硬體加速。將腦電訊號轉換為時間-頻率-振幅的三維資料以得到更多資訊，最後以腦波確認其可行性。

摘要(英)

This paper discusses a new method of electroencephalography (EEG) signal feature extracting. The EEG signal is a non-linear non-stationary signal. Com-pared with the Fourier transform with hypothetical signal, the Hilbert Huang Transform (HHT) is more suitable for processing such signals, but it takes more operating time.
The analysis using the traditional method needs to take the data through the sensor and transmit it to the computer for feature extraction, this process takes more time and it also takes more time when transmitting large amount of data. If the feature extraction can be performed first through the firmware to reduce the data dimension or directly complete the brain-computer interface by the firmware, the efficiency can be greatly improved. In this paper, we analysis EEG signals with less resources on the firmware, the target is to simplify the process and the complexity of the operation.
A field-programmable gate Array (FPGA) is used to implement hardware ac-celeration with the algorithm proposed in this paper. The EEG signal is con-verted into time-frequency-amplitude three-dimensional data for more infor-mation, and finally the brain wave is used to confirm its feasibility.

關鍵字(中)

★ 希爾伯特-黃轉換
★ 經驗模態分解
★ 現場可程式邏輯閘陣列
★ 腦電圖

關鍵字(英)

★ HHT
★ EMD
★ FPGA
★ EEG

論文目次

摘要 I
ABSTRACT II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章緒論 1
1.1 研究動機與目的 1
1.2 大綱 1
第二章瞬時頻譜及現有方法 2
2.1 前言 2
2.2 HHT簡介 3
2.2.1 EMD與LMD 3
2.3 討論 9
2.3.1 邊界條件 10
2.3.2 混模問題 11
2.4 本論文設計方法 13
第三章基於FPGA架構實現特徵提取EEG 27
3.1 硬體架構 27
3.2 極值點提取單元 28
3.3 均值包絡線運算單元 29
3.4 特徵提取單元 29
第四章實驗結果與未來展望 32
4.1 DATA介紹 32
4.2 轉換結果 33
4.3 未來展望 46
第五章結論 48
參考文獻 49

參考文獻

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[5] Cichocki’s Lab (Lab. for Advanced Brain Signal Processing), " Datasets"
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[7] J. Xiong, S. Tian and C. Yang, "Analog fault feature extraction and classifi-cation based on LMD and LVQ neural network," 2017 ICAMMAET, Chen-nai, India, Feb. 2017
[8] A.A. Prince, S. Ganesh and P.K. Verma, "Efficient implementation of empir-ical mode decomposition in FPGA Using Xilinx System Generator," IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, Oct. 2016
[9] W.O. Tatum, "Ellen R. Grass Lecture: Extraordinary EEG," Neurodiagnos-tic Journal, vol 54, pp. 3–21, Mar. 2014
[10] K.A. Elif, Bayraktaroglu Zubeyir, Gurvit Hakan, Keskin Yasemin and Emre Mura, "Comparative analysis of event-related potentials during Go/NoGo and CPT: Decomposition of electrophysiological markers of re-sponse inhibition and sustained attention," Brain Research, vol 1104, pp. 114-128, Aug. 2016
[11] Luay Fraiwan and Khaldon Lweesy, "Neonatal sleep state identification using deep learning autoencoders," IEEE 13th International Colloquium on Signal Processing & its Applications (CSPA), pp.10-12, Mar. 2017

指導教授

徐國鎧(Kuo-Kai Shyu)

審核日期

2018-8-21

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