憶阻式內容循址記憶體之測試

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鄧力瑋(Li-Wei Deng) 查詢紙本館藏

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電機工程學系

論文名稱

憶阻式內容循址記憶體之測試
(Testing of Memristor-Based Content Addressable Memories)

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摘要(中)

內容循址記憶體 (Content-Addressable Memory, CAM) 為一種被廣泛運用在
網絡系統中的元件。為了解決與功耗和面積的問題，許多非揮發性的內容循址記
憶體因此被提出。在這些非揮發性的內容循址記憶體中，憶阻式的內容循址記憶
體是一個不錯的候選元件。但是，現存的憶阻式內容循址記憶體其細胞架構和半
導體式內容循址記憶體其細胞架構有很大的不同，而且，也因為憶阻器引發了一
些錯誤機制。因此，憶阻式內容循址記憶體需要有效的測試方法及其錯誤模型。
在此篇論文，我們透過加入各種不同的電子性缺陷，像是電阻性開路、電阻
性短路、電晶體開路、電晶體短路、電阻式橋接，來定義 5T-2R 憶阻式內容定
址記憶體。然後，我們提出了一種行軍式測試演算法 March-MCAM 來涵蓋我們
所定義的 5T2R 憶阻式內容循址記憶體之比對性錯誤模型。 March-MCAM 需
要 6N 的寫入指令及 (14N+2B) 的比對指令來涵蓋一個 NxB-bit 5T-2R 憶阻式
內容循址記憶體的比對性錯誤模型，在此 14N 代表的是兩個比對指令需要執行
7 次。但是，憶阻式內容循址記憶體有許多不同的細胞架構，若要人工手動去一
一測試，會需要相當多的時間。因此，在論文的第二個部分我們提出了一個內容
循址記憶體自動化測試的方法。最後，我們提出了內容循址記憶體的行軍式測試
產生之演算法自動化的方法。此方法運用了讀與搜尋偵測之等效 Read-Compare
Detection Equivalence (RCDE) 來減少產生時間。最後，分析結果顯示，產生所需
要的時間比沒用 RCDE 的方法快了 2 倍。

摘要(英)

Content addressable memory (CAM) is one widely used component in network systems.
Recently, memristor-based CAMs have been proposed to cope with the power and area issues
of conventional CMOS-based CAMs. Among them, memristor-based CAM is considered as a
good candidate. However, existing memristor-based CAM cell structures are much different
from conventional CMOS-based CAM structures. Also, the fabrication process of memristor
device may induce new failure mechanisms. Therefore, effective fault modeling and testing
techniques for memristor-based CAMs are imperative.
In this thesis, we define comparison faults for 5T-2R memristor-based ternary CAMs
(mrTCAMs) by injecting the electrical defects of resistive open, short, transistor stuck-on,
transistor stuck-open, and bridge. Then, a March-like test, March-MCAM, is proposed to
cover the comparison faults of 5T-2R mrTCAMs. The March-MCAM requires 6N Write
operations and (14N+2B) Compare operations to cover 100% comparison faults of an N×B-
bit 5T-2R mrTCAM array where 14N represents 2 compare operaitons are executed 7 times.
However, different cell structures were proposed to realize mrTCAMs. It is time-consuming
to manually do the fault modeling and test algorithm design. Therefore, we also propose an
automation method for the fault modeling of CAMs. Finally, we propose a test algorithm
generation method for CAMs. The proposed method uses the Read-Compare Detection
Equivalence (RCDE) concept to reduce the test generation time. Analysis results show that
the proposed method can achieve about 2 times of generation time reduction in comparison
with the method without using RCDE concept.

關鍵字(中)

★ 憶阻器
★ 內容循址記憶體

關鍵字(英)

★ Memristor
★ CAM
★ TCAM
★ Fault model

論文目次

1 Introduction 1
1.1 Memristor . 1
1.2 Memristor-based CAMs . 2
1.2.1 CAMs . 2
1.2.2 Nonvolatile CAMs 3
1.3 Testing of CMOS-based CAMs and Memristor Memories . 4
1.4 Thesis Organization 5
2 Fault Modeling and Testing of Memristor-based TCAMs 6
2.1 Motivation . 6
2.2 NMOS-access mrTCAM Cell . 6
2.3 Electrical Fault Models of mrTCAM 8
2.3.1 Traditional Faults . 9
2.4 Test Algorithm for mrTCAMs 20
2.5 Relationship Between Defect and Defect Size 23
2.6 Summary . 24
3 Fault Modeling Automation for CAMs 25
3.1 Motivation . 25
3.2 Proposed Automatic Fault Modeling Method 25
3.2.1 Platform of Automatic Fault Modeling . 25
3.2.2 Flow of Automatic Fault Modeling . 26
3.2.3 Defect Simulation Flow 29
3.2.4 Classification . 29
3.3 Simulation Result . 32
3.3.1 Case Study 33
3.3.2 Analysis on Different Cell Structures 38
3.4 Summary . 43
4 Automatic Test Algorithm Generation for CAMs 44
4.1 Motivation . 44
4.2 Test Algorithm Generation by Simulation (TAGS) . 44
4.3 Algorithm Generation Strategy . 45
4.3.1 BCAM-Flow 46
4.3.2 TCAM-Flow 48
4.4 C-TAG Structure . 50
4.5 CAM Test Algorithm Generation 52
4.5.1 C-TAG Fault Simulator . 52
4.5.2 C-TAG Flow . 61
4.6 Simulation Result . 68
4.7 Summary . 72
5 Conclusion and Future Work 76
5.1 Conclusion . 76
5.2 Future Work 77

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指導教授

李進福(Jin-Fu Li)

審核日期

2018-8-21

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