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姓名	蔡名彥(Ming-Yan Tsai)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	加強型氮化鎵電晶體之閘極電流與電容研究和長時間測量分析
相關論文	★ 電子式基因序列偵測晶片之原型 ★ 增強型與空乏型砷化鋁鎵/砷化銦鎵假晶格高電子遷移率電晶體: 元件特性、模型與電路應用 ★ 使用覆晶技術之微波與毫米波積體電路 ★ 注入增強型與電場終止型之絕緣閘雙極性電晶體佈局設計與分析 ★ 以標準CMOS製程實現之850 nm矽光檢測器 ★ 600 V新型溝渠式載子儲存絕緣閘雙極性電晶體之設計 ★ 具有低摻雜Ｐ型緩衝層與穿透型Ｐ＋射源結構之600V穿透式絕緣閘雙極性電晶體 ★ 雙閘極金氧半場效電晶體與電路應用 ★ 空乏型功率金屬氧化物半導體場效電晶體 設計、模擬與特性分析 ★ 高頻氮化鋁鎵/氮化鎵高速電子遷移率電晶體佈局設計及特性分析 ★ 氮化鎵電晶體 SPICE 模型建立 與反向導通特性分析 ★ 新型加強型氮化鎵高電子遷移率電晶體之電性探討 ★ 氮化鎵蕭特基二極體與高電子遷移率電晶體之設計與製作 ★ 整合蕭特基p型氮化鎵閘極二極體與加強型p型氮化鎵閘極高電子遷移率電晶體之新型電晶體 ★ 垂直型氧化鎵蕭特基二極體於氧化鎵基板之製作與特性分析 ★ 氮化鋁鎵/氮化鎵高電子遷移率電晶體之佈局分析及功率放大器研製
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   至系統瀏覽論文 ( 永不開放)
摘要(中)	本論文為探討p型氮化鎵閘極氮化鋁鎵/氮化鎵高電子遷移率電晶體(HEMT)之閘極特性研究，因為p型氮化鎵提升閘極下方的能障，能有效抑制閘極電流。由過去的文獻可知，電子與電洞穿越於閘極可用熱穿越與Poole – Frenkel發射穿越來進行，因此本實驗將量測元件在不同溫度時的漏電流，觀察電流在低正偏壓、高正偏壓與負偏壓時載子的行為。發現在正偏壓時，電流會出現兩種不同的斜率，可知在高偏壓時有電洞注入並壓抑漏電流，接著估算在各偏壓時的能障值，在高正偏壓時的能障約為0.7 V。後續分析閘極電容在1MHz時隨溫度的變化，發現隨溫度上升電容值的最大值會下降且會在更高的偏壓下發生，此機制推測是跟元件閘極之蕭特基位障相關。 一般來說，因閘極無絕緣層的緣故，高電子遷移率電晶體操作閘極偏壓都不超過7 V，若施加過大電壓閘極位障將承受不住載子穿越，使得閘極控制能力減弱。因此本篇論文將針對高閘極偏壓時元件的可靠度進行討論，在三種偏壓下觀察元件之存活時間，並使用韋伯分佈之數值方法推測元件在正常操作時之存活時間。之後進行變溫量測，分析在不同的溫度下，元件的可靠度與穩定度，並觀察在施加高電壓的壓力前後電流的變化，發現在高偏壓的環境下元件的臨界電壓會往負方向偏移，且經實驗驗證在崩潰後元件的閘極與源極之間會有一個電阻特性的電流路徑。
摘要(英)	This thesis is to investigate the gate characteristics of p-type GaN gated AlGaN/Ga N High Electron Mobility Transistor (HEMT), because p-type GaN can improve the energy barrier under the gate, effectively suppressing the gate current. It is known from the literature that electron and hole tunneling can be performed by thermal tunneling and Poole-Frenkel emission tunneling. Therefore, this experiment will measure the leakage current of devices at different temperatures. When the current is low positive bias, high positive bias and negative bias, the behavior of the carriers are found. When the positive bias is applied, the current will have two different slopes. It is known that there is hole injection and suppression of leakage at high bias. Current, then estimate the energy barrier value at each bias voltage. The energy barrier at high positive bias is about 0.7 V. The subsequent analysis of the gate capacitance changes with temperature at 1 MHz. It is found that the maximum value of the capacitance value decreases with temperature and will be occurs at higher bias, this mechanism is presumed to be related to the Schottky barrier of the gate electrode. In general, due to the absence of an insulating layer on the gate, the gate bias of the high electron mobility transistor does not exceed 7 V. If an excessive voltage gate is applied, the carriers will not be able to withstand the traverse, resulting in weakly gate control, so this thesis will discuss the reliability of devices with high gate bias, observe the survival time of the devices under three kinds of bias, and use the numerical method of Weibull distribution to estimate the survival time of the devices during normal operation. Then, the temperature measurement was carried out to analyze the reliability and stability of the devices at different temperatures, and the change of the current before and after the high voltage stress was observed. It was found that the threshold voltage of the devices would have a negative shift in the high bias environment. Offset, and experimentally verified that there is a resistance current path between the gate and source of the device after the crash.
關鍵字(中)	★ 氮化鎵 ★ 閘極電流 ★ 閘極電容 ★ 可靠度 ★ 長時間量測	關鍵字(英)
論文目次	摘要 I Abstract II 目錄 IV 圖目錄 VI 表目錄 X 第一章 緒論 1 1.1 前言 1 1.2 氮化鎵材料特性 2 1.3 加強型氮化鎵電晶體之閘極特性文獻回顧 4 1.4 研究動機與目的 24 1.5 論文架構 25 第二章 加強型氮化鎵之閘極I-V與C-V測量分析 1 2.1 前言 26 2.2 元件閘極漏電流之量測與分析 26 2.2.1 元件結構與基本特性 26 2.2.2 閘極漏電流量測 28 2.2.3 載子穿越機制 28 2.2.4 閘極漏電流分析 31 2.3 元件閘極電容量測與分析 42 2.4 結論 45 第三章 加強型氮化鎵長時間量測 46 3.1 前言 46 3.2 加強型氮化鎵元件長時間量測 46 3.3 以韋伯分布推測存活時間 50 3.4 加壓前後之閘極電流與臨界電壓分析 55 3.5 結論 60 第四章 結論 61 參考文獻 62
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指導教授	辛裕明(Yue-Ming Hsin)	審核日期	2019-8-21
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