研究製程變異度對負電容場效電晶體與電路的類比性能之影響

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盧宜君(Yi-Chun Lu) 查詢紙本館藏

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電機工程學系

論文名稱

研究製程變異度對負電容場效電晶體與電路的類比性能之影響
(Investigation of Analog Performance for Negative Capacitance SOI MOSFETs and Circuits considering Intrinsic Process Variations)

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摘要(中)

隨著元件尺寸微縮，具低功耗與高性能特性的元件對於現階段積體電路系統是非常重要，降低操作電壓(Supply Voltage)為降低功耗最有效的解決方法之一。而當降低元件操作電壓時，伴隨著降低元件導通電流(On Current)的缺點，因此具有陡峭次臨界擺幅(Subthreshold Swing)與較高開關電流比值(Ion/Ioff ratio)的負電容場效電晶體(Negative Capacitance Field Effect Transistor, NCFET)，為有機會實現低功率消耗與高性能的前瞻元件之一。
第一部分利用TCAD結合穩態的Landau-Khalatnikov方程式，建立了負電容絕緣層上矽場效電晶體的數值模擬流程架構，分析負電容絕緣層上矽場效電晶體的類比品質因數(Analog Figures-of Merit)，並且考慮變異度對於類比品質因數的影響。在類比品質因數的研究中，負電容絕緣層上矽場效電晶體比絕緣層上矽場效電晶體在轉導(Transconductance, gm)、汲極電流轉換效率(Drain Current Efficiency, gm/Id)皆有顯著提升，並表現出相近的截止頻率(Cutoff Frequency, ft)。接著，探討類比品質因數考慮變異度對於負電容絕緣層上矽場效電晶體和絕緣層上矽場效電晶體的汲極輸出電阻(Drain Output Conductance, gd)、轉導、汲極電流轉換效率與截止頻率之影響，變異度包含線邊緣粗糙變異度(Line Edge Rouoghness, LER)和金屬功函數變異度(Work Function Variation, WFV)。負電容絕緣層上矽場效電晶體在考慮線邊緣粗糙度所引起的汲極電流與汲極輸出電阻變異度，小於考慮金屬功函數變異度所引起的汲極電流與汲極輸出電阻變異度，然而對於轉導、汲極電流轉換效率及截止頻率變異度為相反的趨勢，這是由於考慮線邊緣粗糙度的電壓增益的變異度比考慮金屬功函數的電壓增益變異度大。
第二部份為負電容絕緣層上矽場效電晶體考慮表面陷阱電荷(Interface Trap Charge, Nit)與閘極長度變化應用於類比電路的研究，此部分利用TCAD軟體考慮Landau-Khalatnikov的模型在混合模式(Mixed-Mode)下模擬其電路特性。探討三種電路，分別為電容放電(Discharging Circuit)、類比開關(Analog Switch)以及電流鏡(Current Mirror)。相較於絕緣層上矽場效電晶體，負電容絕緣層上矽場效電晶體提升電容放電速度、具有較小的導通電阻(On Resistance)，並改善平坦度(Flatness)，以及降低輸出電流(Iref)誤差率。另外，負電容絕緣層上矽場效電晶體可以抑制變異度對放電速度、導通電阻以及輸出電流的變化，研究結果顯示負電容絕緣層上矽場效電晶體可以簡化堆疊式電流鏡電路，同時保持與堆疊式電流鏡電路相近的輸出電流準確度。

摘要(英)

As the semiconductor device scales, device with ultra-low power and high performance is essential to vary-large-scale integration system. Lowering the supply voltage is the most effective way to reduce the power consumption. However, transistors show worse drive current and performance with the supply voltage lowering. Therefore, device with steep subthreshold slope is essential in order to achieve high Ion/Ioff ratio and low power as supply voltage scales. Negative capacitance field effect transistor (NCFET) is promising candidate to achieve low-power consumption and high performance.
In the first part, we establish the numerical simulation framework for NCFET by using TCAD coupled with Landau-Khalatnikov equation, and then we analyze the variability of analog figures-of merit (FOMs) for negative capacitance FETs. Negative capacitance SOI MOSFETs (NC-SOI MOSFETs) exhibit larger transconductance (gm), larger drain current efficiency (gm/Id), and comparable cutoff frequency (ft) compared with the SOI MOSFETs. For the variability study, we analyze Id-Vds characteristics and analog figures-of merit (FOMs) for NC-SOI MOSFETs and SOI MOSFETs considering line-edge roughness (LER) and work function variation (WFV). For NC-SOI MOSFETs, LER induced Id and drain output conductance (gd) variations are smaller than WFV induced Id and gd variations, because LER induced σVt is smaller than WFV induced σVt. However, the variability of other analog figures-of merit such as gm, gm/Id, and ft for NC-SOI MOSFETs considering LER and WFV show different trend as compared to σVt. NC-SOI MOSFETs considering WFV exhibit smaller σgm, σ(gm/Id), and σft than NC-SOI MOSFETs considering LER, due to the smaller WFV induced internal voltage gain (Av) variations.
In the second part, we analyze the circuit performance of NC-SOI and SOI MOSFETs considering the impact of interface trap charge (Nit) and gate length (Lg) variations. NC-SOI analog circuits are analyzed by TCAD mixed mode simulations employing Landau-Khalatnikov equation. Compared to SOI MOSFETs, NC-SOI MOSFETs show significant improvements in discharging time (ts), lower on resistance (Ron) and better Ron flatness, and better output current (Iout) matching. For NC-SOI MOSFETs, the discharging time, Ron of switch circuit, and Iout of current mirror show superior immunity to Nit and Lg variations compared to the SOI counterparts. Moreover, NC-SOI current mirror can significantly reduce the circuit complexity and area penalty while maintaining adequate mirroring accuracy compared to the stacked SOI current mirror.

關鍵字(中)

★ 鐵電材料
★ 負電容絕緣層上矽電晶體
★ 類比品質因數
★ 類比電路
★ 變異度
★ 線邊緣粗糙變異度
★ 金屬功函數變異度
★ 表面陷阱電荷

關鍵字(英)

論文目次

摘要 I
Abstract III
致謝 V
圖目錄 IX
第一章導論 1
1.1 背景與相關研究 1
1.1.1 鐵電材料與負電容場效電晶體 2
1.2 研究動機 12
1.3 論文架構 13
第二章負電容場效電晶體考慮變異度對於類比品質因數之影響 14
2.1 前言 14
2.2 元件結構與模擬參數 15
2.3 模擬架構 17
2.3.1 線邊緣粗糙變異度(Line Edge Roughness) 20
2.3.2 金屬功函數變異度(Work Function Variation) 22
2.4 分析變異度對於元件特性之影響 24
2.5 分析變異度對於類比品質因數之影響 32
2.5.1 分析變異度對於轉導特性之影響 32
2.5.2 分析變異度對於汲極電流轉換效率之影響 36
2.5.3 分析變異度對於截止頻率之影響 39
2.6 結論 42
第三章負電容場效電晶體考慮變異度應用於類比電路之影響 43
3.1 前言 43
3.2 元件結構與模擬參數 44
3.3 變異度對於臨界電壓之影響 46
3.4 考慮變異度於類比電路之影響 49
3.4.1 電容放電(Discharging Circuit) 49
3.4.2 類比開關(Analog Switch) 52
3.4.3 電流鏡(Current Mirror) 55
3.5 結論 60
第四章總結 61
參考文獻 64

參考文獻

[1] I.R. Committee, "International Roadmap for Devices and Systems," 2016 Edition. More Moore white paper.
[2] J. Valasek, "Piezo-Electric and Allied Phenomena in Rochelle Salt," Physical Review, vol. 17, pp. 475, 1921.
[3] Sayeef Salahuddin and Supriyo Dattat, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, No. 2, pp. 405-410, 2008.
[4] C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin and C. Hu, "Low power negative capacitance FETs for future quantum-well body technology," 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013, pp. 1-2.
[5] E. Ko, J. W. Lee and C. Shin, "Negative Capacitance FinFET with Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V," in IEEE Electron Device Letters, vol. 38, no. 4, pp. 418-421, April 2017.
[6] M. H. Lee et al., "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," 2016 IEEE International Electron Devices Meeting, 2016, pp. 12.1.1-12.1.4.
[7] E. Ko, H. Lee, Y. Goh, S. Jeon and C. Shin, "Sub-60-mV/decade Negative Capacitance FinFET with Sub-10-nm Hafnium-Based Ferroelectric Capacitor," in IEEE Journal of the Electron Devices Society, vol. 5, no. 5, pp. 306-309, Sept. 2017. doi: 10.1109/JEDS.2017.2731401
[8] Y. Li, Y. Kang and X. Gong, "Evaluation of Negative Capacitance Ferroelectric MOSFET for Analog Circuit Applications," in IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 4317-4321, Oct. 2017.
[9] Y. Liang et al., "Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET," in IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3909-3914, Sept. 2018.
[10] Y. Liang, X. Li, S. K. Gupta, S. Datta and V. Narayanan, "Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model," in IEEE Transactions on Electron Devices, vol. 65, no. 12, pp. 5525-5529, Dec. 2018.
[11] X. Li et al., "Enabling Energy-Efficient Nonvolatile Computing with Negative Capacitance FET," in IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3452-3458, Aug. 2017.
[12] W. You, P. Su and C. Hu, "Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits," in IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 2004-2009, April 2019.
[13] E. T. Breyer, H. Mulaosmanovic, T. Mikolajick and S. Slesazeck, "Reconfigurable NAND/NOR logic gates in 28 nm HKMG and 22 nm FD-SOI FeFET technology," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 28.5.1-28.5.4.
[14] A. I. Khan, "Negative Capacitance for Ultra-low Power Computing. PhD thesis," University of California at Berkeley, 2015.
[15] C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin and C. Hu, "Low power negative capacitance FETs for future quantum-well body technology," 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013, pp. 1-2.
[16] J. Seo, J. Lee and M. Shin, "Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications," in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1793-1798, April 2017.
[17] Y. Li, Y. Lian, K. Yao, G. S. Samudra, "Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory", Solid-State Electron., vol. 114, pp. 17-22, Dec. 2015.
[18] G. Pahwa et al., "Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation," in IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986-4992, Dec. 2016.
[19] H. Agarwal, P. Kushwaha, J. P. Duarte, Y.-K. Lin, A. B. Sachid, M.-Y. Kao, Y.-L. Chang, S. Salahuddin, and C. Hu, "Engineering Negative Differential Resistance in NCFET for Analog Applications," IEEE Transactions on Electron Deivces, vol. 65, no. 5, pp. 2033-2039, May 2018.
[20] V. P.-H. Hu, Y.-C. Lu and P.-C. Chiu, "Investigation of Analog Performance for Negative Capacitance SOI MOSFET considering Line-Edge Roughness," IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, US, June 2018.
[21] A. K. Saha, P. Sharma, I. Dabo, S. Datta and S. K. Gupta, "Ferroelectric transistor model based on self-consistent solution of 2D Poisson′s, nonequilibrium Green′s function and multi-domain Landau Khalatnikov equations," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 13.5.1-13.5.4.
[22] J. Seo, J. Lee and M. Shin, "Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications," in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1793-1798, April 2017.
[23] H. Ota, T. Ikegami, J. Hattori, K. Fukuda, S. Migita and A. Toriumi, "Fully coupled 3-D device simulation of negative capacitance FinFETs for sub 10 nm integration," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 12.4.1-12.4.4.
[24] V. P.-H. Hu, P.-C. Chiu, A. B. Sachid and C. Hu, "Negative capacitance enables FinFET and FDSOI scaling to 2 nm node," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 23.1.1-23.1.4.
[25] H. Zhou et al., "Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect," 2018 IEEE Symposium on VLSI Technology, Honolulu, US, 2018, pp. 53-54.
[26] Z. Zhang et al., "FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2," in IEEE Electron Device Letters, vol. 40, no. 3, pp. 367-370, March 2019.
[27] V. P.-H. Hu, M. -L. Fan, P. Su and C. -T. Chuang, "Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp. 335-342, Sept. 2011.
[28] H. P. Lee and P. Su, "Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs," in IEEE Electron Device Letters, vol. 38, no. 10, pp. 1492-1495, Oct. 2017.
[29] V. P.-H. Hu, P.-C. Chiu and Y.-C. Lu, "Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 295-302, 2019.
[30] T. Dutta, G. Pahwa, A. Agarwal and Y. S. Chauhan, "Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits," in IEEE Electron Device Letters, vol. 39, no. 1, pp. 147-150, Jan. 2018.
[31] G. Karbasian et al., "Ferroelectricity in HfO2 thin films as a function of Zr doping," 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, pp. 1-2.
[32] A. Asenov, S. Kaya and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," in IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
[33] N. Agrawal, Y. Kimura, R. Arghavani and S. Datta, "Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications," in IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3298-3304, Oct. 2013.
[34] H. F. Dadgour, K. Endo, V. K. De and K. Banerjee, "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design," in IEEE Transactions on Electron Devices, vol. 57, no. 10, pp. 2515-2525, Oct. 2010.
[35] K. Ohmori et al., "Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates," 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-4.
[36] J. P. Duarte et al., "Compact models of negative-capacitance FinFETs: Lumped and distributed charge models," 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 30.5.1-30.5.4.
[37] C. Auth, "45nm high-k + metal gate strain-enhanced CMOS transistors," 2008 IEEE Custom Integrated Circuits Conference, San Jose, CA, 2008, pp. 379-386.
[38] C. Lin, A. I. Khan, S. Salahuddin and C. Hu, "Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics," in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2197-2199, May 2016.
[39] A. I. Khan, C. W. Yeung, Chenming Hu and S. Salahuddin, "Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation," 2011 International Electron Devices Meeting, Washington, DC, 2011, pp. 11.3.1-11.3.4.
[40] A. D. Gaidhane, G. Pahwa, A. Verma and Y. S. Chauhan, "Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor," in IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 2024-2032, May 2018.
[41] Y.-C. Lu and V. P.-H. Hu, "Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations," 2019 IEEE Silicon Nanoelectronics Workshop (SNW), Koyto, Japan, June 2019.
[42] H. Lee, K. Tseng and P. Su, "Interface discrete trap induced variability for negative capacitance FinFETs," 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2018, pp. 1-2.
[43] Sentaurus TCAD, O-2018-6 Manual.
[44] Suman Datta, "Negative Capacitance Ferroelectric Transistors: A Promising Steep Slope Device Candidate?," 2015, https://nanohub.org/resources/23011.

指導教授

胡璧合

審核日期

2019-9-26

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