| 摘要(英) |
The design of analog/mixed-signal (AMS) integrated circuits is getting complex as technology advances. Speeding up the simulation involving with digital and analog circuits becomes a key to solve the system verification issues for SOC designs. Building their behavioral models for analog circuit blocks by hardware description language is an efficient approach for verifying AMS systems. If each analog circuit can be transformed into its corresponding behavioral model automatically, the simulation time for the analog part can be greatly reduced. Therefore, an efficient structure analysis flow is desired to automatically extract the building blocks, no matter it is an analog block or digital block, in a mixed-signal design based on the given circuit netlist. Using a special encoding scheme, the digital and analog blocks in the netlist can be identified quickly and replaced automatically by the corresponding behavior models built in the library. However, in previous works, different circuits may have duplicate structure in digital circuit analysis. In analog circuit analysis, the identified blocks may have overlap issues, too. In this thesis, we extend the previous structure analysis platform to consider these issues. In the case of duplicate structure, additional encoding is added in digital circuit analysis to verify the accuracy of the port orders of the circuit. In analog circuit analysis, a bottom-up hierarchical structure recognition approach is proposed to accurately determine which the circuit structure belongs to. This approach solves the structure overlap problem and raise the abstraction level of the identified models simultaneously. As shown in the experiments, the efficiency and accuracy of the identification results can be improved to reduce the extra efforts for system verification. |
| 參考文獻 |
[1] http://www.cadence.com/eu/Documents/MicrosoftPowerPoint ToT2013openend.pdf
[2] https://verificationacademy.com/verification-horizons/october-2012-volume-8-issue-3/improving-analog-mixed-signal-verification-productivity
[3] P. Wambacq, F. Fernández, G. Gielen, W. Sansen, and A. Rodríguez-Vázquez, “Efficient Symbolic Computation of Approximated Small-signal Characteristics” IEEE Journal. Solid-State Circuits, vol. 30, pages. 327–330, Mar 1995.
[4] 樓禹慷， “自動辨識混合訊號電路中數位區塊之方法”，中央大學碩士論文，July 2016
[5] 林慶和， “適用於類比電路區塊之解析式行為模型產生器及數位化建模技術”，中央大學碩士論文，Oct 2016
[6] 王綉文， “適用於混合訊號設計的自動化電路區塊降為模型產生器” ， 中央大學碩士論文，July 2014
[7] T. Massier, “The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis”, IEEE Computer-Aid Design of Integrated Circuit and Systems, December 2008.
[8] https://zh.wikipedia.org/wiki/SPICE
[9] CIC 國家晶片系統設計中心, “Hspice Tutorial”
[10] 宋伶彥，“用於類比電路行為模型產生器之非迴歸式模型校準方法”，中央大學碩士論文，June 2017
[11] 王俊，“自動辨識混合訊號電路中構成區塊及RLC元件之方法 ” ，中央大學碩士論文，Jan 2017
[12] 郭啓鍊，“以機器學習模型協助正確辨識混合訊號電路中電路區塊之方法 ” ，中央大學碩士論文，July 2018
[13] Hao Li, Fanshu Jiao and Alex Doboli, “Analog circuit topological feature extraction with unsupervised learning of new sub-structures”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
[14] M. Ohlrich, C. Ebeling, E. Ginting, and L. Sather, “SubGemini: Identifying Subcircuits Using a Fast Subgraph Isomorphism Algorithm”, Proceedings of Design Automation Conference, pp. 31-37, June 1993.
[15] Z. Ling, and D. Y. Y. Yun, “An Efficient Subcircuit Extraction Algorithm by Resource Management” , 2nd International Conference on ASIC, pp. 9-14, Oct 1996.
[16] L. Huang, T. Y. Jiang, J. Y. Jou, H.L. Huang, “An Efficient Logic Extraction Algorithm Using Partitioning and Circuit-Encoding,” in Proceeding International Symposium on Circuits and Systems, 2004.
[17] N. P. Keng, and D. Y. Y. Yun, “A Planning Scheduling Methodology for the Constrained Resource Problem”, Proceedings 1989 International Joint Conference on Artificial Intelligence, pp. 20-25, Aug 1989. |
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