提升負電容穿隧場效電晶體效能之最佳化設計

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林宏翰(Hung-Han Lin) 查詢紙本館藏

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電機工程學系

論文名稱

提升負電容穿隧場效電晶體效能之最佳化設計
(Optimization of Negative-Capacitance Vertical-Tunnel FET for Performance Enhancement)

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摘要(中)

現今CMOS技術，為了達到低功率消耗之應用，如物聯網( Internet of Things, IoT) 科技以及穿戴式元件等，降低供應電壓(VDD)以達到降低功率消耗，一直是CMOS技術主要的挑戰。傳統金氧半場效電晶體(MOSFET)，在室溫下由於電流受波茲曼分佈影響，使得次臨界擺幅(Subthreshold Swing, SS)無法低於60mV/decade。隨後，穿隧場效電晶體(Tunneling field-effect transistors, TFETs)被提出以解決傳統金氧半場效電晶體對於次臨界擺幅的限制。穿隧場效電晶體的電流由能帶穿隧(Band-to-band tunneling)機制所主導，因此，其次臨界擺幅可以低於60mV/decade，在低供應電壓下，可以表現出高效率的電流-電壓轉換特性(IDS-VGS)。三五族異質接面穿隧場效電晶體因其較小的等效位能障(Effective tunneling barrier height)，使得穿隧機率提高，進而提升導通電流。因三五族材料之能態密度較低，在高操作電壓時，三五族穿隧電晶體仍然不易達到高導通電流，但在低操作電壓下，其導通電流仍可優於傳統金氧半場效電晶體。本篇論文利用TCAD建立三五族穿隧場效電晶體及負電容穿隧場效電晶體模型，研究與分析其結構及鐵電材料對於元件電性的影響，以優化三五族穿隧場效電晶體及負電容穿隧場效電晶體之導通電流與次臨界擺幅，並提出最佳化之元件結構。
第一部分為GaAs0.49Sb0.51/In0.53Ga0.47As負電容垂直穿隧場效電晶體的元件最佳化設計，在閘極加入鐵電層(Ferroelectric layer)，利用其負電容效應(Negative Capacitance effect)，搭配穿隧層(Tunnel layer)的設計，使提升導通電流，在此章節，我們討論閘極與源極重疊長度(Gate-to-source overlap length)、穿隧層厚度(Tt)和穿隧層摻雜濃度(N++ doping concentration)的影響，以最佳化元件結構。在VDD = 0.5V下，最佳化的負電容垂直穿隧場效電晶體表現出低漏電流 (Ioff = 10pA/?m)與高導通電流(Ion = 405?A/?m)，與平面式超薄層(Ultra-thin-body, UTB)穿隧場效電晶體相比，負電容垂直穿隧場效電晶體具有較高的電導與截止頻率。
第二部分為GaAs0.4Sb0.6/In0.65Ga0.35As 垂直奈米線穿隧場效電晶體結構之最佳化分析，利用非均勻式通道設計(Non-uniform diameter)，以及閘極與汲極欠疊式(Gate-to-drain underlap)設計抑制雙極性漏電流，同時也利用穿隧層設計以提升導通電流。此外，我們亦分析穿隧層厚度(Tt)、非均勻通道厚度(TDC)、源/汲極摻雜濃度(Source/drain doping concentrations)以及閘極與源極重疊長度(Lsov)的影響。相較於平面式超薄層穿隧場效電晶體，垂直奈米線穿隧場效電晶體的導通電流(Ion = 236?A/?m)有兩倍的提升，其漏電流(Ioff = 5.5×10-10 ?A/?m)並降低59.8倍。

摘要(英)

Power scaling is one of the major challenges in modern CMOS technology for ultra-low power applications, such as emerging IoT (Internet of Things) technologies and wearable devices. Lowering the supply voltage (VDD) is an efficient technique to achieve ultra-low power consumption for circuits. Device with steep subthreshold slope is essential in order to achieve energy-efficient switching and low leakage power as VDD scaling. Conventional MOSFET exhibits the lower-bound limitation of subthreshold swing (SS) which is about 60 mV/dec at room temperature. In order to tackle this problem, tunneling field-effect transistors (TFETs) have been actively explored [1].
III-V heterojunction TFETs with smaller effective tunneling barrier heights show enhanced on current due to the increased tunneling probability. However, due to the low density of states, III-V heterojunction TFETs exhibit lower on current than the conventioinal MOSFETs at high VDD. However, III-V heterojunction TFETs still show better performance than the conventional MOSFETs at low VDD owing to its steep subthreshold slope.
In the first part of this thesis, the device design and analog performance of GaAs0.49Sb0.51/In0.53Ga0.47As negative-capacitance vertical-tunnel FET (NCVT-FET) are analyzed compared with the vertical-tunnel FET (TFET). The optimized device design of NCVT-FET is proposed to maximize its vertical tunneling over the corner tunneling to reduce its average subthreshold swing. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. The impacts of gate-to-source overlap length, tunnel layer thickness, and N++ doping concentration in the tunnel layer have been investigated. The optimized NCVT-FET exhibits small Ioff (10pA/?m) and large Ion (405?A/?m) at VDD = 0.5V with 14mV/decade subthreshold swing over 4 decades of current. Moreover, the optimized NCVT-FET shows higher transconductance gm,max (+92%), higher gm/IDS, and larger cutoff frequency fT,max (+75%) compared to TFET.
In the second part of this thesis, we analyze the heterojunction GaAs0.4Sb0.6/In0.65Ga0.35As TFET with vertical nanowire structure and non-uniform diameter design (V-NW TFET with non-uniform diameter). A tunnel layer (Tt) is inserted between the gate and source regions for improving the on currents, and the non-uniform diameter thickness is used for suppressing the leakage current (Imin). The bandgap widening induced by quantum confinement is considered in the simulations. The leakage currents can be suppressed by using thinner diameter thickness of the drain/channel junction (TDC), and the gate-to-drain underlap design is used to further reduce the ambipolar leakage. The impacts of Tt, TDC, source and drain doping concentrations, and gate-to-source overlap length (Lsov) on the V-NW TFET have been investigated. Compared with the ultra-thin-body (UTB) TFET, the proposed V-NW TFET with non-uniform diameter (thin TDC) exhibits 2 times larger Ion (236 ?A/μm) due to the increased line tunneling area, and 59.8 times lower leakage current (5.5 × 10-10 ?A/μm).

關鍵字(中)

★ 負電容場效電晶體
★ 穿隧場效電晶體
★ 異質接面
★ III-V族材料
★ 鐵電材料
★ 垂直奈米線
★ 非均勻通道厚度
★ 雙極性漏電流

關鍵字(英)

★ Negative capacitance
★ Tunneling field-effect transistors
★ heterojunction
★ III-V
★ ferroelectric
★ vertical nanowire
★ non-uniform diameter
★ ambipolar leakage

論文目次

摘要 I
Abstract III
致謝文 V
圖目錄 X
表目錄 XV
第一章導論 1
1.1 相關背景研究 1
1.2 研究動機 11
1.3 論文架構 12
第二章負電容垂直穿隧場效電晶體結構優化及類比特性分析 13
2.1 前言 13
2.2 負電容垂直穿隧場效電晶體結構元件設計 19
2.2.1 元件模擬參數 19
2.2.2 電容效應對於垂直穿隧場效電晶體之影響 23
2.3 元件結構參數之研究 26
2.3.1 閘極與源極間重疊長度之影響 26
2.3.2 穿隧層厚度之影響 28
2.3.3 穿隧層摻雜濃度之影響 30
2.4 Landau–Khalatnikov參數之分析 34
2.5 最佳化結構之電性分析 39
2.6 最佳化結構之類比特性分析 43
2.7 結論 46
第三章垂直奈米線三五族異質接面穿隧場效電晶體元件設計以用於效能提升 49
3.1 前言 49
3.2 垂直奈米線三五族異質接面穿隧場效電晶體 50
3.2.1 元件結構參數 50
3.2.2 元件之IDS-VGS與次臨界擺幅特性比較 52
3.3 元件結構參數之分析 54
3.3.1 非均勻通道厚度之影響 54
3.3.2 穿隧層厚度之影響 56
3.3.3 汲極與源極摻雜濃度之影響 59
3.3.4 閘極與源極間重疊長度之影響 60
3.4 結論 61
第四章結論 63
參考文獻 65

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指導教授

胡璧合(Pi-Ho Hu)

審核日期

2019-9-26

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