異質整合共閘極N型砷化銦鎵與P型鍺鰭式場效電晶體於矽基板之研究

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呂翎華(Ling-Hua Lu) 查詢紙本館藏

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電機工程學系

論文名稱

異質整合共閘極N型砷化銦鎵與P型鍺鰭式場效電晶體於矽基板之研究
(Heterogeneous Integration of Common Gate-stack n-InGaAs and p-Ge Fin Field-Effect Transistors on Si)

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摘要(中)

本論文研究是以高電子遷移率之砷化銦鎵和高電洞遷移率之鍺作為通道材料，開發互補式金屬-氧化物-半導體場效電晶體(CMOS FETs)，並整合於低成本且易量產之矽基板上。此研究採用選擇性磊晶方式，使用有機金屬化學蒸氣沉積系統於鍺奈米溝槽中依序成長砷化鋁銦緩衝層與砷化銦鎵通道層。研究結果顯示，砷化鋁銦在高溫成長之沉積速率較慢且易形成島狀形貌；若以先低溫再高溫的二階段成長方式，則可獲得連續性較佳之磊晶形貌。
本研究亦以原子層沉積系統沉積氮化鋁/氧化鋁雙層結構作為鍺與砷化銦鎵共閘極高界電係數材料，採用快速熱氧化和 HF 浸泡進行沉積前表面處理，探討不同退火溫度下之金氧半界面特性。在氮氣環境下以350℃退火兩分鐘，鍺與砷化銦鎵金氧半電容以電導法萃取之界面捕陷密度(Dit)分別為3.59×1011eV-1cm-2和5.29×1011eV-1cm-2。在沉積閘極金屬TiN與歐姆金屬Ti/AlSiCu後，在氮氣95%和氫氣5%的環境中以350℃退火五分鐘，鍺電容Dit可降至1.95×1011eV-1cm-2，100 kHz下之遲滯電壓偏移∆VFB從0.13V降至0.078V；砷化銦鎵電容Dit降至4.79×1011eV-1cm-2，遲滯電壓偏移從0.18V降低至0.056V，表示此退火條件有效降低界面缺陷。
結合N型通道磊晶設計以及共閘極製程，砷化銦鎵FinFET在Wfin=50nm 與Lg=60nm最大電流密度為0.29μA/μm、S.S為558mV/dec以及Ion/Ioff ratio為1.35×10^2，閘極漏電密度大約為10^-6 μA/μm。接著透過後製程的方式，蝕刻元件下方的鍺塊材以減少漏電流路徑，SS可下降至394mV/dec.且Ion/Ioff ratio 則可提升至4.35×10^2。鍺FinFET亦透過相同的蝕刻方式，每減少1μm2面積的鍺塊材可下降約18.5µA漏電流，亦證實通道下方鍺塊材為造成元件漏電的主要路徑之一。

摘要(英)

This study aims at fabricating a hybrid complementary metal-oxide-semiconductor (CMOS) structure consisting of high electron mobility InGaAs and high hole mobility Ge channels on Si substrates. The heterogeneous integration is implemented by selective area epitaxy of InGaAs channel and an InAlAs buffer on nano-patterned Ge templates by metal-organic chemical vapor deposition (MOCVD). This shows that the growth rate of the InAlAs buffer at high temperature is lower than that at low temperature and tend to form islands on the surface. Surface morphology is significantly improved by using a two-step growth method, i.e the growth is performed at low temperature and followed by high temperature growth.
A common gate-stack process for both InGaAs and Ge channels is developed in this work. AlN/Al2O3/InGaAs and AlN/Al2O3/Ge MOS capacitors (MOSCAPs) are fabricated for investigating the interfacial characteristics. Rapid thermal oxidation (RTO) followed by dipping the samples in HF solution is used for surface treatment. The post-deposition annealing temperature is optimized based on their capacitance-voltage characteristics. The Ge and InGaAs MOSCAPs annealed in N2 ambient at 350 ℃ for two minutes exhibit an interface trap density of 3.59×1011eV-1cm-2 and 5.29×1011 eV-1cm-2, respectively. The interface trap density canbe further reduced by 45% and 10% for Ge and InGaAs MOSCAPs respectively after post-metal gate (TiN) annealing (PMA) at 350 ℃ for five minutes. In addition, the ∆VFB decreases from 0.13 V to 0.078 V for Ge MOSCAPs and 0.18 V to 0.056 V for InGaAs MOSCAPs.
Combining the epitaxial growth and common gate processes, InGaAs FinFETs with Lg/Wfin of 80 nm/120 nm exhibit a maximum drain current of 0.29 µA/µm, a subthreshold swing of 558 mV/dec, and an Ion/Ioff ratio of 1.35×10^2. The gate leakage current is well below 10^-6 µA/µm. After removing the Ge layer under the InGaAs channel, the subthreshold swing of the InGaAs FinFETs decreases from 558 mV/dec to 394 mV/dec with an increase in Ion/Ioff ratio from 1.35×102 to 4.35×10^2 . A similar trend has also been observed on Ge FinFETs, indicating the Ge bulk layer under the channel is the main leakage current path in these devices.

關鍵字(中)

★ 鰭式場效電晶體
★ 選擇性磊晶
★ 共閘極
★ 砷化銦鎵
★ 鍺

關鍵字(英)

★ FinFET
★ Selective Area Epitaxy
★ Common Gate-stack
★ InGaAs
★ Ge

論文目次

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 viii
表目錄 xi
第一章緒論 1
1.1 前言 1
1.2 研究動機 3
1.2.1 材料選擇 3
1.2.2 高界電係數之金氧半電容發展 5
1.2.3 III-V/Ge場效電晶體之發展 8
1.3 論文架構 10
第二章 MOVCD選擇性成長砷化銦鎵通道於鍺模板 11
2.1 前言 11
2.2 Ge/Si 基板製作 12
2.3 砷化鋁銦磊晶成長條件 15
2.3.1 二次成長對磊晶結果之分析 15
2.3.2 腔體壓力以及溫度對磊晶結果影響分析 19
2.4 砷化銦鎵成長條件分析 21
2.5 選擇性磊晶整合砷化銦鎵與鍺通道之製程 24
2.5.1 磊晶前製程步驟 24
2.5.2 磊晶前表面處理結果比較 26
2.6 本章總結 28
第三章共閘極氮化鋁/氧化鋁/鍺與砷化銦鎵金氧半電容之研究 29
3.1 前言 29
3.2 金氧半電容原理與參數介紹 31
3.2.1 金氧半電容操作原理 31
3.2.2 氧化物與半導體界面介紹 33
3.2.3 金氧半電容參數計算 35
3.3 試片製備與實驗步驟 37
3.3.1 基板結構 37
3.3.2 實驗步驟 37
3.4 界面處理條件對鍺與砷化銦鎵金氧半電容電性變化之探討 40
3.4.1 沉積後退火(PDA)對砷化銦鎵金氧半電容影響之分析 40
3.4.2 沉積後退火(PDA)對鍺金氧半電容影響之分析 43
3.4.3 金屬後退火(PMA) 對砷化銦鎵/鍺金氧半電容影響之分析 46
3.5 鍺與砷化銦鎵金氧半電容之界面分析 50
3.6 本章總結 51
第四章 P型鍺與N型砷化銦鎵鰭式場效電晶體 52
4.1 前言 52
4.2 選擇性磊晶砷化銦鎵鰭式場效電晶體製作步驟 53
4.3 砷化銦鎵鰭式場效電晶體特性分析與討論 57
4.3.1 元件特性分析 57
4.3.2 掏空鍺塊材後元件特性分析 60
4.4 選擇性磊晶鍺鰭式場效電晶體製作流程 62
4.5 鰭式場效電晶體特性分析與討論 66
4.5.1 元件特性分析 66
4.5.2 PTS製程之元件特性分析 67
4.5.3 掏空鍺塊材後元件特性分析 69
4.6 本章總結 71
第五章總結 72
參考文獻 74

參考文獻

[1] Yong Huang, Jing-Ping Xu,Lu Liu, Zhi-Xiang Cheng,Pui-To Lai and Wing-Man Tang, “Improved interfacial and electrical properties of Ge MOS capacitor with ZrON/TaON,” Appl.Phys. Letters .,vol. 111, no. 5, 053501, 2017.
[2] Mengnan Ke, Mitsuru Takenaka and Shinichi Takagi, “Reduction of Slow Trap Density in Al2O3/GeOxNy/n-Ge MOS Interfaces by PPN-PPO Process,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 66, no. 12, p. 5060-5064, 2019.
[3] Huy Binh Do, Quang Ho Luc, Minh Thien Huu Ha, Sa Hoang Huynh, Tuan Anh Nguyen, Yueh Chin Lin and Edward Yi Chang, “Study of the interface stability of the metal (Mo, Ni, Pd)/HfO2/AlN/InGaAs MOS,” AIP Advances, vol. 7, no. 8, 2017.
[4] Su-Keun Eom, Min-Woo Kong, Myoung-Jin Kang , Jae-Gil Lee, Ho-Young Cha , and Kwang-Seok Seo, "Enhanced Interface Characteristics of PA-ALD HfOxNy/InGaAs MOSCAPs Using IPA Oxygen Reactant and Cyclic N2 Plasma," IEEE ELECTRON DEVICE LETTERS, vol. 39, no. 11, p. 99, 2018.
[5] W.C. Lee, P. Chang , T.D. Lin , L.K. Chu , H.C. Chiu , J. Kwo and M.Hong, “InGaAs and Ge MOSFETs with high k dielectrics,”Microelectronic Engineering, vol. 88, p.336, 2011.
[6] C.H. Fu, Y.H. Lin , W.C. Lee , T.D. Lin , R.L. Chu , L.K. Chu , P. Chang , M.H. Chen ,W.J. Hsueh, S.H. Chen f, G.J. Brown , J.I. Chyi , J. Kwo and M. Hong, “Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs,” Microelectronic Engineering, vol. 147, p. 330, 2015.
[7] L. Czornomaz, E. Uccelli, M. Sousa, V. Deshpande, V. Djara, D. Caimi, M. D. Rossell, R. Erni and J. Fompeyrine, “Confined Epitaxial Lateral Overgrowth (CELO): A Novel Concept for Scalable Integration of CMOS-compatible InGaAs-on-insulator MOSFETs on Large-Area Si
Substrates,” VLSI, p.172-173 , 2015.
[8] Gerben Doornbos, Martin Holland, Gerogios Vellianitis, Mark J. H. Van Dal, Blandine Duriez, Richard Oxland, Aryan Afzaliva, Ta-Kun Chen, Gordon Hsiech,, "High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates," vol. 4, no. 5, 2016.
[9] Clarissa Convertino, Cezar Zota, Heinz Schmid, Daniele Caimi, Marilyne Sousa , “Replacement Metal Gate InGaAs-OI FinFETs by Selective Epitaxy in Oxide Cavities, EUROSOI-ULIS, p.1-4 , 2019.
[10] N. Waldron, C. Merckling, L. Teugels, P. Ong, F. Sebaai, K. Barla, N., “Replacement fin processing for III–V on Si: From FinFets to nanowires,” Solid-State Electronics, vol. 115, p. 81-91, 2016.
[11] M. L. Huang, S. W. Chang, M. K. Chen, C. H. Fan, H. T. Lin, C. H. Lin, “In0.53Ga0.47As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate,” VLSI, p. 240, 2015.
[12] M. Yamaguchi, T. Nishioka and M. Sugo, “Analysis of strained layer superlattice effects on dislocation density reduction in GaAs on Si substrates,” Appl. Phys. Lett, vol. 54, no. 1, p. 54, 1989.
[13] K. Prabhakaran, F. Maeda, Y. Watanabe and T. Ogino, “Thermal decomposition pathway of Ge and Si oxides: observation of a distinct difference, ” vol. 369, no. 1-2, p. 289-292, 2000.
[14] G. Wanga, N. D. Nguyen, M.R. Leys, R. Loo, G. Brammertz,O. Richard, H. Bender, J. Dekoster, M. Meuris, M.M. Heyns, M. Caymax, “Selective Epitaxial Growth of InP in STI Trenches on Off-axis Si (001) Substrates,” ECS Transactions, vol. 27, no. 1, p.959-964, 2010.
[15] B. Kunert, W. Guo, Y. Mols, R. Langer, K. Barla, “Integration of III/V Hetero-Structures by Selective Area Growth on Si for Nano- and Optoelectronics,” ECS Transactions, vol. 75, no. 8, p. 409-419, 2016.
[16] Chyi-Yeou Soong, “Gasdynamic Characteristics and Thermal-Flow Design of Metal Organic Chemical Vapor Deposition Reactors for Semiconductor Thin-Fil,” vol. 25, no. 3, 2003.
[17] Ilkay Demir, Sezai Elagoz, “Interruption time effects on InGaAs/InAlAs superlattices of quantum cascade laser structures grown by MOCVD,” Superlattices and Microstructures, vol. 100, p. 723-729, 2016.
[18] Shiyan Li, Xuliang Zhou, Xiangting Kong, Mengke Li, Junping Mi, Jing Bian,Wei Wang, Jiaoqing Pan, “Evaluation of growth mode and optimization of growth parameters for GaAs epitaxy in V-shaped trenches on Si,” Journal of Crystal Growth,vol. 426, no. 15, p.147-152, 2015.
[19] Kazumasa Hiramatsu, Katsuya Nishiyama, Masaru Onishi, Hiromitsu Mizutani,Mitsuhisa Narukawa, Atsushi Motogaito, Hideto Miyake, Yasushi Iyechika, Takayoshi Maeda, “Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO) , ” Journal of Crystal Growth, vol. 224, no. 1-4, p. 316-626, 2000.
[20] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-k gate dielectrics:Current status and materials properties considerations,” J. Appl. Phys, vol. 89, no. 10, 2001.
[21] B. Zeghbroeck, Principles of Semiconductor Devices, 2011.
[22] E. H. Nicollian and A. Goetzberger, “The Si-SiO2 interface-Electrical properties as determined by the metal-insulator-silicon conductance technique,” Bell System Technology Journal, vol .46, p. 1055, 1967.
[23] 徐賢名, 氧化鉿 /氧化鋁 /銻化鎵金氧半結構製備與界面缺陷分析, 國立中央大學, 2014.
[24] 許哲瑋, 氧化鉿∕砷化銦金氧半結構之製備及其界面與電性研究, 國立中央大學, 2012.
[25] C. Weiland, “Passivation of In0.53Ga0.47As/ZrO2 interfaces by AlN atomic layer deposition process,” Appl. Phys, vol. 114, no. 3, 2013.
[26] G. Miceli, and A. Pasquarello, “Defect levels at GaAs/Al2O3 interface:As-As dimer vs.Ga dangling bond,” Applied Surface Science, vol. 291, no.1, pp. 16-19, 2014.
[27] H. Matsubara, “Evidence of low interface trap density in GeO2/Ge metal-oxide semiconductor structures fabricated by thermal oxidation,” Appl. Phys. Lett, vol. 93, no. 3, 2008.
[28] F. Bellenger, C. Merckling, J. Penaud, M. Houssa, M. Caymax, M.Meuris, “Molecular dynamics simulation comparison of atomic scale intermixing at the amorphous Al2O3/semiconductor interface for a-Al2O3/Ge, a-Al2O3/InGaAs, and a-Al2O3/InAlAs/InGaAs,” Elsevier
B.V., vol. 603, no.21 , p. 3191-3200, 2009.
[29] M. K. Bera, “TiO2/GeOxNy stacked gate dielectrics for Ge-MOSFETs,” Semicond. Sci. Technol, vol. 22, no. 12, 2007.
[30] Y.Hwang, R,Engel-Herbert,N.G.Rudawski,and S.Stemmer, “Analysisof trap state densities at HFO2/In0.53Ga0.47As interfaces,” Appl. Phys. Lett, vol. 96, no.10, 2010.
[31] Y. Yuan, “A Distributed Model for Border Traps in Al2O3 − InGaAs MOS Devices,” IEEE ELECTRON DEVICE LETTERS, vol. 32, no. 4, 2011.
[32] K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, “Process Integration Technology and Device Characteristics of CMOS FinFET on Bulk Silicon Substrate with sub-10 nm Fin Width and 20 nm Gate Length,” IEEE, 2005.
[33] G. Eneman, G. Hellings, A. De Keersgieter, N. Collaert, A. Thean, “Quantum-Barriers and Ground-Plane Isolation: A Path for Scaling Bulk-FinFET Technologies to the 7 nm-node and Beyond,” IEDM, vol. 13, p. 320, 2013.

指導教授

綦振瀛(Jen-Inn Chyi)

審核日期

2020-8-18

推文