應用於記憶邏輯運算之非揮發性鐵電場效電晶體記憶體

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何敦義(Tun-Yi Ho) 查詢紙本館藏

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電機工程學系

論文名稱

應用於記憶邏輯運算之非揮發性鐵電場效電晶體記憶體
(Ferroelectric FET Non-Volatile Memory for Logic-in-Memory Applications)

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摘要(中)

隨著人工智慧(Artificial Intelligence)與物聯網(Internet of Things)的蓬勃發展，傳統的記憶體由於記憶端(Memory)與處理端(Process)的低資料傳輸量與高功耗影響，且處理端的運算速度大於記憶端的讀寫速度，進而有馮諾伊曼瓶頸(Von Neumann Bottleneck)的現象發生。近年來，二氧化鉿(HfO2)快速發展在鐵電材料的應用，夾層為二氧化鉿的鐵電場效電晶體有效緩解該瓶頸，藉由記憶體單元內邏輯運算的特性來消除數據移動上能量與時間消耗。
第一部分利用鐵電場效電晶體(Ferroelectric FET, FeFET)結構，使用TCAD軟體並結合穩態的Preisach方程式模擬出記憶體視窗(Memory Window)特性，邏輯組合輸入於閘極端，分別為鐵電層極化的寫入與讀取電壓高低狀態，判別出電流的高低值，並藉由源極(Source)與背閘極(Back-Gate)電壓造成記憶體視窗(正反掃Ids-Vgs圖形)左右平移，最後由上拉電路轉換為輸出電壓值，並成功實現NOR與NAND邏輯閘特性。我們全面且量化的探討NOR與NAND邏輯閘的設計空間(Design Space)，並加入鐵電參數的變異度去深入分析，可發現在NOR與NAND邏輯閘特性中，使用背閘極電壓有較廣的設計空間。接著由最佳化設計值的源極與背閘極電壓在NAND邏輯閘去分析其延遲時間(Propagation Delay)、功率延遲積(Power Delay Product)與能量延遲積(Energy Delay Product)，研究結果發現最佳化背閘極在延遲時間、功率延遲積和能量延遲積都有較佳的改善優勢。
第二部分使用分離式閘極鐵電場效電晶體(Split-Gate FeFET)去實現出NOR、NAND與XNOR邏輯閘。分離式閘極鐵電場效電晶體有兩個閘極，一個閘極給予定值的電壓使記憶體視窗(正反掃Ids-Vgs圖形)能夠左右平移，而另一個閘極藉由鐵電層極化寫入與讀取電壓高低狀態，去實現NOR與NAND邏輯閘，與FeFET使用的源極與背閘極電壓參數調變方式不同，透過閘極調變全面且量化的分析設計空間。分離式閘極鐵電場效電晶體去實現AOI (AND-OR-INVERTER)邏輯電路，其中包含NAND、NOT與NOR特性實現。相較於傳統的AOI邏輯電路，透過分離式閘極鐵電場效電晶體來取代第一級的NAND，能使總電晶體數目減少。並且在兩顆FeFET串聯實現XNOR邏輯中，單顆分離式閘極鐵電場效電晶體亦能實現XNOR邏輯閘，由分析結果可得知分離式閘極鐵電場效電晶體的寫入電壓低於前者，可有效降低功率消耗，改善能量效率。

關鍵字：鐵電材料、馮諾伊曼瓶頸、鐵電場效電晶體、分離式閘極鐵電場效電晶體、非揮發性記憶體、記憶體視窗、記憶邏輯運算、變異度、設計空間

摘要(英)

With the successive development of Artificial Intelligence (AI) and Internet of Thing (IoT), the communication between memory and processing units becomes a serious challenge due to high power consumption and low data throughput. In general, the processing speed is faster than the read/write speed of the memory, which leads to the Von Neumann bottleneck. Moreover, with the recent discovery of ferroelectricity in HfO2, the novel ferroelectric FET (FeFET) based non-volatile memory is alleviated the Von Neumann bottleneck by computing inside the logic memory units and eliminating the energy-intensive and time-consuming data movement.
In the first part, TCAD simulations for FeFET are coupled with Preisach model, and then we analyze and simulate the characteristic of memory window. The two inputs used to perform the logic functionality of the FeFET can be obtained through ferroelectric polarization state and gate voltage, whereas the potential at source and back-gate are utilized to shift the transfer characteristics towards higher (or lower) gate bias to obtain all the logic states corresponding to input combinations. The circuit used to perform NOR or NAND logic operation consists of single FeFET with a pull up resistor in series. The functionality of pull-up resistor is to transform the current state to the output voltage. It is shown that NOR and NAND logic functionality can be realized with 1T FeFET, and then we can analyze the design space comprehensively and quantitatively by applying source and back-gate voltage. We also analyze the impact of ferroelectric parameter variations on the design space, and we can know the back-gate voltage providing wider design space in the nominal and ferroelectric variations. The comparisions of propagation delay, power delay product (PDP), and energy delay product (EDP) of FeFET NAND logic gate with optimal source and back-gate voltage have been analyzed. The optimal back-gate voltage shows improvement in delay time, PDP, and EDP with optimal source voltage.
In the second part, we use split-gate FeFET to achieve NOR, NAND, and XNOR logic functionality. In contrast to single gate FeFET, split-gate FeFET uses two front gates to achieve the logic operation. One gate is fixed at constant voltage to shift the Ids-Vgs curve towards lower (or higher) gate bias, and another gate is provided with ferroelectric polarization state and gate voltage as the inputs. This method achieves NOR and NAND logic function by modulating one gate, and the design space of the gate voltage in split-gate FeFET is analyzed comprehensively and quantitatively. To further demonstrate the advantages of using split-gate device structure, the thesis explores the AOI (AND-OR-INVERTER) circuit. The AOI circuit uses the NAND, NOT, and NOR logic functions. Results highlight that split-gate FeFET can replace conventional NAND logic function in the AOI logic circuit, and thus it reduces the number of transistors in the conventional AOI circuit. Moreover, the results obtained from AOI circuit designed with the split-gate are comparable with conventional AOI circuit. Furthermore, the thesis explores the XNOR logic operation using split-gate and conventional FeFET. Results show that split-gate FeFET lowers the writing voltage in XNOR logic function.
Keywords: Ferroelectric, Von Neumann bottleneck, ferroelectric FET, split-gate FeFET, non-volatile memory, memory window, logic in memory, variability, design space

關鍵字(中)

★ 鐵電材料
★ 馮諾伊曼瓶頸
★ 鐵電場效電晶體
★ 分離式閘極鐵電場效電晶體
★ 非揮發性記憶體
★ 記憶體視窗
★ 記憶邏輯運算
★ 變異度
★ 設計空間

關鍵字(英)

★ Ferroelectric
★ Von Neumann bottleneck
★ ferroelectric FET
★ split-gate FeFET
★ non-volatile memory
★ memory window
★ logic in memory
★ variability
★ design space

論文目次

摘要 I
Abstract III
致謝 V
圖目錄 XI
表目錄 XVI
第一章導論 1
1.1 背景與相關研究 1
1.1.1 鐵電材料與非揮發性鐵電場效電晶體發展介紹 2
1.1.2 非揮發性鐵電場效電晶體操作應用 6
1.1.3 記憶邏輯運算介紹 9
1.2 研究動機 13
1.3 論文架構 14
第二章鐵電電晶體探討源極與背閘極的設計空間並探討變異度的影響與功率能量差異 15
2.1 前言 15
2.2 模擬模型Preisach Model介紹 16
2.3 鐵電場效電晶體記憶體視窗 19
2.4 元件結構與模擬模型架構 21
2.5 透過記憶體視窗平移達成邏輯閘與設計空間 23
2.5.1 邏輯閘OR與NOR實現結果 27
2.5.2 邏輯閘透過源極實現AND與NAND結果 28
2.5.3 邏輯閘透過背閘極實現AND與NAND結果 29
2.5.4 記憶體視窗平移過多導致邏輯閘失敗例子 30
2.5.5 最佳化源極與背閘極定義與設計空間邊界值 32
2.5.6 功率與能量延遲積在最佳化源極與背閘極 35
2.6 分析變異度對於設計空間的影響 37
2.6.1 鐵電參數變異度對於NOR的設計空間 37
2.6.2 鐵電參數變異度對於NAND的設計空間 40
2.7 結論 42
第三章分離式閘極鐵電場效電晶體操作於邏輯閘電路量化且實現 43
3.1 前言 43
3.2 記憶體視窗 45
3.3 元件結構與模擬參數 47
3.4 分離式閘極鐵電場效電晶體於陣列中 48
3.5 分離式閘極鐵電電晶體實現XOR與XNOR 51
3.5.1 分離式閘極鐵電場效電晶體優勢於XNOR中 52
3.5.2 寫入極化電壓差異在XNOR邏輯閘 57
3.6 分離式閘極鐵電場效電晶體實現邏輯閘 59
3.6.1 分離式閘極鐵電場效電晶體實現OR與NOR 60
3.6.2 分離式閘極鐵電場效電晶體實現AND與NAND 62
3.6.3 記憶體視窗平移太多造成失敗 63
3.6.4 閘極1調變的設計空間與最佳化值 64
3.7 分離式閘極鐵電場效電晶體實現AOI電路 65
3.8 結論 68
第四章總結 69
參考文獻 72

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指導教授

胡璧合(Pi-Ho Hu)

審核日期

2020-8-19

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