應用於IEEE 802.3bp™-2016車用乙太網路收發機之等化器、回音消除器與時序回復電路設計與整合

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姓名

陳衍祐(Yen-Yu Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於IEEE 802.3bp™-2016車用乙太網路收發機之等化器、回音消除器與時序回復電路設計與整合
(Design and Integration of Equalizer, Echo Canceller and Timing Recovery Circuit for IEEE 802.3bp™-2016 Automotive Ethernet Transceiver)

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至系統瀏覽論文 (2026-1-31以後開放)

摘要(中)

隨著行車安全、自動駕駛以及各項行車產品電子化的蓬勃發展，實時AI影像辨識及各項設備間的訊號傳輸需求越來越受重視。本論文依據IEEE 802.3bp™-2016規範標準[1]，設計出車用Gigabit乙太網路傳輸之數位基頻收發機晶片。本論文針對車用乙太網路的環境開發專屬的數位濾波器演算法，著重在通道等化器、回音消除器以及時序回復電路（Timing Recovery Circuit）之演算法及數位電路設計。由於有線車用乙太網路通道屬於擴散通道，因此在等化器演算法採用改良後之較低複雜度的定值模數演算法（Constant Modulus Algorithm, CMA）及決策導向（Decision Directed, DD）演算法來克服通道效應。通道等化器包含前饋等化器（Feedforward Equalizer, FFE）及決策回饋等化器（Decision Feedback Equalizer, DFE），分別用來消除針對前符碼間的干擾及後符碼間的干擾。由於單一雙絞線全雙工傳輸的回音干擾現象，經由演算法推導及模擬結果分析回音消除器之必要性，因而系統更加設計了數位回音消除器。時序回復電路用來克服時脈不匹配效應，透過採用穆勒與姆勒演算法(Mueller and Muller, M&M)的相位檢測方法，加上改良後的可適性消除等化器(Adaptive Canceler Equalizer, ACE)，使得的相位檢測器獲得的通道資訊更接近理想通道響應sinc function。關於硬體實現，先使用Verilog HDL描述與模擬，透過SMIMS VeriEnterprise Xilinx FPGA驗證電路功能，最後經由Design Compiler與IC Compiler來驗證在製程為TSMC-40nm下之電路功能。

摘要(英)

Due to the vigorous development of autonomous vehicles, driving safety and various electrical automotive products, real-time AI image recognition and signal transmission between devices have become increasingly important.
This thesis will present the algorithms and circuits for channel equalization, echo cancellation, and timing recovery to develop an IEEE 802.3bp™-2016 compatible next generation gigabit Ethernet digital baseband transceiver dedicated to an automotive environment. Harmful Inter-Symbol Interference (ISI) will be mitigated by the use of a feedforward equalizer and a decision feedback equalizer, which will deal with the pre-cursor and post-cursor of ISI respectively. At first, the Modified Constant Modulus Algorithm (MCMA) is employed at feedforward equalizer due to the lower complexity, and after the preliminary converge the Decision-Directed algorithm will be applied to both the feedforward equalizer and the decision feedback equalizer. To account for the physical layer specifications of point-to-point full duplex 1 Gb/s Ethernet operations over single balanced twisted-pair copper cables, this system is also designed to include a digital echo canceller. The necessity of the echo canceller is analyzed through algorithm derivation and simulation results. In the part of timing recovery circuit, Phase-Lock Loop (PLL) with the Mueller and Müller algorithm is used to overcome the clock mismatch effect between AD/DA converters. Furthermore, the improved adaptive cancellation equalizer (ACE) is adopted so that the channel information obtained by the phase detector is closer to the ideal channel response.
The hardware is simulated through Verilog HDL. The function is then verified by using SMIMS VeriEnterprise Xilinx FPGA, and implemented in the process of TSMC-40nm through Design Compiler and IC Compiler.

關鍵字(中)

★ 車用乙太網路
★ 通道等化器
★ 回音消除器
★ 時序回復電路

關鍵字(英)

★ automotive ethernet
★ channel qualizer
★ echo canceller
★ timing recovery

論文目次

目錄
摘要 i
Abstract ii
圖目錄 vii
表目錄 x
第一章緒論 1
1.1背景 1
1.2 研究動機 1
1.3 論文貢獻 2
第二章等化器架構介紹 3
2.1 線性等化器（LE） 5
2.2 決策回授等化器（DFE） 6
2.3 可適性等化器（AE） 7
2.4 可適性消除等化器（ACE） 8
第三章等化器演算法介紹 9
3.1 非盲目等化器演算法 9
3.1.1 最小均方（LMS）演算法 9
3.2.1 決策導向（DD）演算法 11
3.2.2 延遲最小均根(Delay-LMS) 12
3.2.3 定值模數演算法（CMA） 14
3.2.4 適用於可適性消除等化器（ACE）演算法 17
第四章回音消除器電路介紹 18
4.1回音消除器電路系統概要 18
4.2回音消除器電路架構與演算法分析 19
4.2.1回音消除器電路架構 19
4.2.2回音消除器演算法 20
第五章時序回復電路介紹 31
5.1 基本介紹 31
5.2時序回復電路系統概要 32
5.2.1 相位檢測器（PD） 33
5.2.2 低通濾波器（LPF） 35
5.2.3 壓控振盪器（VCO） 36
5.3時序回復電路分析 36
第六章系統架構與模擬結果 38
6.1 系統環境 38
6.2系統架構 39
6.3 模擬環境 40
6.3.1 零公尺模擬環境 40
6.3.2 十五公尺模擬環境 41
6.3.3 四十公尺模擬環境 42
6.4 等化器模擬結果 43
6.4.1 零公尺模擬環境等化器模擬結果 43
6.4.2 十五公尺模擬環境等化器模擬結果 45
6.4.3 四十公尺模擬環境等化器模擬 47
6.4 回音消除器電路模擬結果 49
6.4.1 初步模擬 49
6.4.2零公尺模擬環境回音消除器電路模擬結果 53
6.4.3十五公尺模擬環境回音消除器電路模擬結果 55
6.4.4四十公尺模擬環境回音消除器電路模擬結果 57
6.6時序回復電路模擬結果 59
6.6.1零公尺模擬環境時序回復電路模擬結果 59
6.6.1十五公尺模擬環境時序回復電路模擬結果 61
6.6.1四十公尺模擬環境時序回復電路模擬結果 63
6.7系統驗證 65
第七章電路架構與晶片實現 66
7.1 電路設計流程 66
7.2硬體電路介紹 67
7.2.1等化器電路 67
7.2.2回音消除器電路 69
7.2.3時序回復電路 70
7.3模擬驗證 71
7.4晶片設計結果 73
第八章結論與未來展望 75
參考文獻 76

參考文獻

參考文獻
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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2021-1-22

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