以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：5

、訪客IP：3.137.159.251

姓名	李之福(Jhih-Fu Lee)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	二維接地式三角形網格開發及矩陣係數驗證與半導體元件模擬 (2D Grounded Triangle Element and Matrix Coefficient Verification and Its Applications to Semiconductor Device Simulation)
相關論文	★ 表面電漿共振效應於光奈米元件之數值研究 ★ 金氧半電容元件的暫態模擬之數值量測 ★ 雙載子電晶體在一維和二維空間上模擬的比較 ★ 改善後的階層化不完全LU法及其在二維半導體元件模擬上的應用 ★ 一維雙載子接面電晶體數值模擬之驗證及其在元件與電路混階模擬之應用 ★ 階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用 ★ 探討分離式簡化電路模型在半導體元件模擬上的效益 ★ 撞擊游離的等效電路模型與其在半導體元件模擬上之應用 ★ 二維半導體元件模擬的電流和電場分析 ★ 三維半導體元件模擬器之開發及SOI MOSFET特性分析 ★ 元件分割法及其在二維互補式金氧半導體元件之模擬 ★ 含改良型L-ILU解法器及PDM電路表述之二維及三維元件數值模擬器之開發 ★ 含費米積分之高效率載子解析模型及其在元件模擬上的應用 ★ 量子力學等效電路模型之建立及其對元件模擬之探討 ★ 適用於二維及三維半導體元件模擬的可調變式元件切割法 ★ 整合式的混階模擬器之開發及其在振盪電路上的應用
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	本篇論文的主要目是討論二維三角形網格的開發與矩陣係數驗證的重要性，以矩陣係數法為基礎驗證我們所架構的電路模型，並以我們設計的程式去模擬各種類的半導體元件特性。透過對矩陣係數的驗證來確保程式運算時的準確性，再以兩種不同的運算方法來探討同一個運算模型，分別為接地式與非接地式矩陣係數驗證，藉由此方法能夠提高程式運算的精準度。而我們論文中皆採取重心法來驗證三角形網格模型，而此方法好處在於能夠對任意三角形進行驗證，保證程式可符合任意情況。最後，我們以此為出發點模擬出電阻、PN二極體、BJT或其餘特殊半導體元件等模型的電路特性，模擬其特性曲線並與物理意義相互對照，以確保程式的真偽性。
摘要(英)	The main purpose of this thesis is to discuss the importance of the development of 2D triangle element and matrix coefficient verification. Based on the matrix coefficient method, we will verify the circuit model that we have constructed,and use our designed program to simulate various types of semiconductor devices characteristics. Through the verification of the matrix coefficients to ensure the accuracy of the formula calculation, two different calculation methods are used to explore the same calculation model, namely the grounded and the bridged matrix coefficient verification. In our thesis, the center of gravity method is used to verify the triangle mesh model. The advantage of this method is that it can verify any triangle and ensure that the program can satisfy any situation. Finally, we use this triangle model as a starting point to simulate the circuit characteristics of devices such as resistors, PN diodes, BJTs or other special semiconductor devices, simulate their characteristic curves and compare them with physical significance to ensure the authenticity of our program.
關鍵字(中)	★ 矩陣係數驗證 ★ 二維三角形網格 ★ 半導體元件模擬 ★ 接地式 ★ 非接地式 ★ 脊背式電路	關鍵字(英)	★ Matrix Coefficient Verification ★ 2D Triangle Element ★ Semiconductor Device Simulation ★ Grounded ★ Bridged ★ Spine Circuit
論文目次	摘要……………………………………………………………………………………i Abstract………………………………………………………………………………..ii 誌謝…………………………………………………………………………………...iii 目錄…………………………………………………………………………………...iv 圖目錄…………………………………………………………………………………v 表目錄………………………………………………………………………………..vii 第一章 簡介………………………………………………………………………..…1 第二章 電路版矩陣係數驗證………………………………………………………..3 2.1 雙迴圈電路模擬…………………………………………………………….3 2.2非接地式矩陣係數驗證……………………………………………………..4 2.3 接地式矩陣係數驗證……………………………………………………….7 第三章 二維三角形矩陣係數驗證…………………………………………………11 3.1 三角形等效電路之矩陣系數推導……………………………...…………11 3.2 非接地式二維三角形矩陣係數驗證……………………………………...19 3.3 接地式二維三角形矩陣係數驗證………………………………………...29 3.4 非接地式與接地式之比較……………………………………………...…32 第四章 二維半導體元件之應用……………………………………………………35 4.1 二維PN二極體電路特性模擬……………………………………………35 4.2 二維BJT結構分析及其特性曲線………………………………………..39 4.3 脊背凸出物對電阻的影響模擬…………………………………………...44 第五章 結論…………………………………………………………………………46 參考資料……………………………………………………………………………..47
參考文獻	[1]W. G. Feng,” Newton-Raphson method of elastic viscoelastic finite element analysis”, M.S. Thesis,Institute of ME, National Chiao Tung University, Taiwan,Republic of China,1984. [2]T. Z. Huang, ”Finding internal vector from the axis method in arbitrary triangle element for 2-D semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2018. [3]Y. C. Lai,” 1D Matrix Coefficient Verification And Semiconductor Device Simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2020. [4]P. Feldmann , R.A. Rohrer, “Proof of the number of independent Kirchhoff equations in an electrical circuit” ,AT&T Bell Lab., Murray Hill, NJ, USA, 1991. [5]Q. Liu, S. Sutar and A. Seabaugh, “Tunnel diode/transistor differential comparator”, Troy, NY ,USA, 2005. [6]R. L. Boylestad and L. Nashelsky, Electronic Devices and Circuit Theory, Prentice Hall, ninth edition, 2005. [7]T. W. Hsin, ”Potential-Based Modeling of Two Dimensional Workspace Using Several Source Distributions”, M. S. Thesis, Institute of ME,National Chiao Tung University,Taiwan,Republic of China,1993. [8]P. Y. Chang, ”Development of point-added square element and its applications to 2-D semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2016. [9]S. Y. Li, ”Development of four-in-one regular triangle element and its applications to 2D semiconductor device simulation” Nation Central University, Taiwan, Republic of China, 2016. [10]R. A. Jabr, M. Hamad and Y. M. Mohanna, “Newton-Raphson solution of Poisson′s equation in a pn diode”, Int. J. Electrical Eng. Educ,pp.27-29, Jan. 2007. [11]D.A. Neamen, Semiconductor Physics and device 3^{rd}ed. McGraw-Hill Companies Inc.,New Work, 2003. [12]T. Y. Chen,” Derivation and Verification of Electric-Field Equation in Low-high-doping Cylindrical PN Junction”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2020. [13]Y. Y. Li,” Finding internal vector from the Taylor series in tetrahadron element for 3D semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2019. [14]H. Y. Chen,” Finding internal vector from the Taylor series in arbitrary triangle element for 2D semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2019. [15]J. Y. Wu,” 2D matrix coefficient verification and semiconductor device simulation”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2020. [16]Y. C. Lin,” Breakdown simulation of a spherical PN junction in cylindrical coordinates”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, 2012. [17]M. Marrero-Martín, J. García, B. González and A. Hernández, "Circuit models for PN integrated varactors," IEEE Trans, Palma de Mallorca, Spain, pp. 1-4, 2011. [18]Z. A. S. and S. N. A., "Modelling of NPN Bipolar Junction Transistor Characteristics Using Gummel Plot Technique, ”IEEE Trans, Liverpool, UK, pp. 396-400, 2010.
指導教授	蔡曜聰(Yao-Tsung Tsai)	審核日期	2021-7-12
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare