參考文獻 |
[1] Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation”, Asian Test Symposium (ATS′96), pp.258-260, Nov. 1996.
[2] Martin Ester, Hans-Peter Kriegel, Jörg Sander, and Xiaowei Xu. 1996. A density-based algorithm for discovering clusters in large spatial databases with noise. In Proceedings of the Second International Conference on Knowledge Discovery and Data Mining (KDD′96). AAAI Press, 226–231.
[3] M. A. Hearst, S. T. Dumais, E. Osuna, J. Platt and B. Scholkopf, "Support vector machines," in IEEE Intelligent Systems and their Applications, vol. 13, no. 4, pp. 18-28, July-Aug. 1998, doi: 10.1109/5254.708428.
[4] Y. Lecun, L. Bottou, Y. Bengio and P. Haffner, "Gradient-based learning applied to document recognition," in Proceedings of the IEEE, vol. 86, no. 11, pp. 2278-2324, Nov. 1998, doi: 10.1109/5.726791.
[5] Alex Krizhevsky, Ilya Sutskever, and Geoffrey E. Hinton. 2012. ImageNet classification with deep convolutional neural networks. In Proceedings of the 25th International Conference on Neural Information Processing Systems - Volume 1 (NIPS′12). Curran Associates Inc., Red Hook, NY, USA, 1097–1105.
[6] M. Wu, J. R. Jang and J. Chen, "Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets," in IEEE Transactions on Semiconductor Manufacturing, vol. 28, no. 1, pp. 1-12, Feb. 2015, doi: 10.1109/TSM.2014.2364237.
[7] J. Yu and X. Lu, "Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis," in IEEE Transactions on Semiconductor Manufacturing, vol. 29, no. 1, pp. 33-43, Feb. 2016, doi: 10.1109/TSM.2015.2497264.
[8] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, IEEE Transaction on Semiconductor Manufacturing, Vol 31, pp. 309-314, May. 2018.
[9] T. Nakazawa and D. V. Kulkarni, "Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network," in IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 2, pp. 309-314, May 2018, doi: 10.1109/TSM.2018.2795466.
[10] S. Schrunner, O. Bluder, A. Zernig, A. Kaestner and R. Kern, "A Comparison of Supervised Approaches for Process Pattern Recognition in Analog Semiconductor Wafer Test Data," 2018 17th IEEE International Conference on Machine Learning and Applications (ICMLA), Orlando, FL, USA, 2018, pp. 820-823, doi: 10.1109/ICMLA.2018.00131.
[11] K. Kyeong and H. Kim, "Classification of Mixed-Type Defect Patterns in Wafer Bin Maps Using Convolutional Neural Networks," in IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 3, pp. 395-402, Aug. 2018, doi: 10.1109/TSM.2018.2841416.
[12] Agarap, Abien Fred. (2018). Deep Learning using Rectified Linear Units (ReLU).
[13] N. Yu, Q. Xu and H. Wang, "Wafer Defect Pattern Recognition and Analysis Based on Convolutional Neural Network," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 566-573, Nov. 2019, doi: 10.1109/TSM.2019.2937793.
[14] Mengying Fan, Qin Wang and B. van der Waal, "Wafer defect patterns recognition based on OPTICS and multi-label classification," 2016 IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC), Xi′an, China, 2016, pp. 912-915, doi: 10.1109/IMCEC.2016.7867343.
[15] M. Wu, J. R. Jang and J. Chen, "Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets," in IEEE Transactions on Semiconductor Manufacturing, vol. 28, no. 1, pp. 1-12, Feb. 2015, doi: 10.1109/TSM.2014.2364237.
[16] T. Ishida, I. Nitta, D. Fukuda and Y. Kanazawa, "Deep Learning-Based Wafer-Map Failure Pattern Recognition Framework," 20th International Symposium on Quality Electronic Design , Santa Clara, CA, USA, 2019, pp. 291-297, doi: 10.1109/ISQED.2019.8697407.
[17] 呂東穎, “Application of Wafer Map Partition Analysis to Enhance the Salient Pattern IdentificationAnalysis”, 碩士論文, 中央大學, 2019
[18] R. Wang and N. Chen, "Wafer Map Defect Pattern Recognition Using Rotation-Invariant Features," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 596-604, Nov. 2019, doi: 10.1109/TSM.2019.2944181.
[19] Katherine Shu-Min Li,Peter Yi-Yu Liao,Ken Chau-Cheung Cheng,Leon Li-Yang Chen,Sying-Jyan Wang,Andrew Yi-Ann Huang;Leon Chou,Gus Chang-Hung Han,Jwu E. Chen,Hsin-Chung Liang and Chung-Lung Hsu, “Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement”, IEEE Transactions on Semiconductor Manufacturing, Feb. 2021. |