以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：114

、訪客IP：18.224.69.254

姓名	林品安(LIN, PIN-AN)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	使用諧波增強高除數注入鎖定除頻器與四相位考畢子壓控振盪器之研製 (High-Division Injection-Locked Frequency Divider with Harmonic Enhancement and Quadrature Colpitts Voltage-Controlled Oscillator)
相關論文	★ 微波及毫米波切換器及四相位壓控振盪器整合除三 除頻器之研製 ★ 微波低相位雜訊壓控振盪器之研製 ★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統 ★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計 ★ 微波及毫米波行進波切換器之研製 ★ 寬頻低功耗金氧半場效電晶體 射頻環狀電阻性混頻器 ★ 微波與毫米波相位陣列收發積體電路之研製 ★ 24 GHz汽車防撞雷達收發積體電路之研製 ★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究 ★ 高功率高效率放大器與振盪器研製 ★ 微波與毫米波寬頻主動式降頻器 ★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用 ★ 寬頻主動式半循環器與平衡器研製 ★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製 ★ 銻化物異質接面場效電晶體之研製及其微波切換器應用 ★ 微波毫米波寬頻振盪器與鎖相迴路之研製
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	本論文主要探討注入鎖定除頻器與四相位壓控振盪器之研究。在現今的毫米波頻段的收發機系統與雷達中，皆需要一個穩定的本地振盪源，而本地振盪源通常以鎖相迴路來實現。注入鎖定除頻器在鎖相迴路的應用中也相當廣泛，因為注入鎖定除頻器易操作在高頻，使注入鎖定除頻器普遍應用在毫米波頻段的鎖相迴路中的第一級除頻器。 　　第二章首先介紹關於應用在鎖相迴路中各個除頻器的種類，並簡述各個除頻器的運作原理、優缺點以及適合的操作頻段。接著介紹注入鎖定除頻器的注入鎖定原理，利用一個RLC振盪器的等效電路圖闡述當有額外的注入訊號時，RLC振盪器的輸出訊號會與注入訊號產生一相位差，並由此推導出注入鎖定頻寬公式。在此章節中介紹高除數除頻器的電路圖，與其理想的電路模型，並由此電路模型簡述運作模式，讓讀者能夠容易理解此高除數除頻器。透過鎖定頻寬分析中的推導公式的過程中可以得知，增強偶次諧波項可使除頻器之鎖定頻寬增強。此章節透過注入鎖定除頻器與電流模式邏輯除頻器的電路架構，並利用TSMC 0.18 μm CMOS的製程成功設計出K頻段注入鎖定除十除頻器。在注入功率為0 dBm時，鎖定頻寬為22到23.2 GHz，鎖定範圍有1.2 GHz相當於5.3 %的比例頻寬，輸出功率在鎖定範圍皆在-13到-14 dBm之間，電路直流功耗為11.4 mW。 　　第三章使用電流再利用技術來完成V頻段注入鎖定除頻器之設計，此章節電路架構利用串接兩級注入鎖定除頻器來完成高除數除頻器之設計，最後使用TSMC 90 nm GUTM CMOS來完成此章節的電路設計。在章節一開始首先介紹電流再利用之電路架構，並將其使用在注入鎖定除頻器上。由參考文獻中得知二次注入之增強鎖定頻寬技術，並與之結合至電流再利用架構的注入鎖定頻器。在此章節所提出的電流再利用的二次注入電路架構共有兩種，並與無二次注入的除頻器比較其鎖定頻寬，來驗證所提出的電路架構能有效的增強鎖定頻寬。最後在此次的電路設計裡也使用上一章節的諧波增強技術來進一步加強除頻器之鎖定頻寬。在注入訊號功率為0 dBm時，鎖定頻寬為54.8到60.3 GHz，鎖定範圍為5.5 GHz相當於9.6 %的比例頻寬，輸出功率在鎖定時皆在-13到-14 dBm之間，電路的直流消耗為12.3 mW。 　　第四章為K頻段考畢子四相位壓控振盪器。此壓控振盪器利用TSMC 0.18 μm CMOS的製程來完成此章節的電路設計。此章節的壓控振盪器採用考畢子電路架構並利用閘級電感來產生、加強負電阻。此外此章節利用自我注入耦合來達成四相位壓控振盪器之設計。此次電路設計成功實現出在24 GHz附近頻段的輸出訊號，在控制電壓為0 V時，其輸出頻率與輸出功率分別為23.5 GHz, -11 dBm。在控制電壓為1 V時，其輸出頻率與輸出功率分別為22.8 GHz, -10.7 dBm。此次四相位壓控振盪器的可調頻率範圍大約為700 MHz。相位雜訊在控制電壓為0.6 V時有最好的相位雜訊值為-96 dBc/Hz @ 1MHz offset。以其中一個輸出為基準去和其他三個輸出做相位相減，在差動輸出的相位誤差為0.9度。而90度與270度輸出的相位誤差為40到50度。
摘要(英)	This thesis focuses on the study of injection-locked frequency dividers and quadrature voltage-controlled oscillators (QVCO). A stable local oscillator is necessary for the modern transceiver and radar system up to millimeter-wave bands. The local oscillator can be usually realized using a phase locked loop (PLL). The injection-locked frequency dividers (ILFD) are also employed in the millimeter-wave PLL due to their high speed and low dc power consumption, and the ILFD can be adopted as the first-stage frequency divider in the PLL. 　　Several types of frequency divider for the PLL are introduced in Chapter 2, and they are briefly described with the operation principle and advantages and disadvantages among the presented frequency dividers. Then, the injection locked principle of ILFD is introduced. An injection-locked equation is derived based on an equivalent resistance-inductance-capacitance (RLC) circuit for the oscillator. The phase difference between the oscillator and the injection signal is resulted when the external signal is injected into the oscillator. Thee circuit diagrams and the ideal circuit models of the high-division dividers will be briefly presented with the operation principle. From the locking-range analysis, the locking bandwidth can be enhanced by increasing the even-harmonic term of the oscillator. In this chapter, a 0.18-μm CMOS divide-by-10 ILFD is successfully designed using the harmonic-enhancement technique. With an injection power of 0 dBm, the measured locking range is from 22 to 23.2 GHz with an overall locking range of 1.2 GHz and a 5.3% fractional bandwidth. The measured output power is higher -14 dBm over the locking range. The dc power consumption of the ILFD is 11.4 mW. 　　In Chapter 3, a current-reused technique is employed in a V-band ILFD. The proposed ILFD is composed of two stages of frequency dividers to achieve a high division ratio of 6. The circuit design of the presented ILFD is first presented with some theoretical calculations and simulations. Furthermore, a double-injection technique is also employed in the ILFD circuit design to enhance the locking range, and the ILFD is realized using a TSMC 90-nm CMOS process. As compared with prior art, the proposed ILFD features wide locking range and low dc power. With an input power of 0 dBm, the measured locking range is 54.8 to 60.3 GHz, and the measured output is higher -14 dBm over the locking range. The ILFD has an overall locking range of 5.5 GHz and a 9.6% fractional bandwidth. The DC consumption of the V-band ILFD is 12.3 mW. The measured oscillation frequency is from 22.8 to 23.5 GHz as the controlled voltage is from 0 to 1 V, and the measured output power is higher than -11 dBm over the tuning 　　A K-band Colpitts QVCO is presented in Chapter 4. The presented QVCO is designed using a TSMC 0.18-μm CMOS process. The oscillation core is implemented using Colpitts topology to lower phase noise. Two differential Colpitts oscillators are coupled using a self-injection technique to achieve the quadrature generation. The measured oscillation frequency is from 22.8 to 23.5 GHz as the control voltage is from 0 to 1 V, and the measured output power is higher than -11 dBm over the tuning range. The measured minimum phase noise of the QVCO is -96 dBc/Hz at 1-MHz offset when the control voltage is 0.6 V. The measured phase error is between 40 to 50 degree among the four quadrature outputs.
關鍵字(中)	★ 高除數 ★ 注入鎖定除頻器 ★ 四相位壓控振盪器	關鍵字(英)	★ High-Division ★ ILFD ★ QVCO
論文目次	摘要 III Abstract V 目錄 IX 圖目錄 XI 表目錄 XVI 第一章 緒論 1 1.1 研究動機及背景 1 1.2 相關研究發展 2 1.3 論文架構 3 1.4 論文貢獻 4 第二章 增強偶次諧波項K頻段注入鎖定除十除頻器 5 2.1 簡介 5 2.2 除頻器架構概述 6 2.3 注入鎖定原理與注入鎖定除頻器 9 2.3.1 注入鎖定原理[42][48][49] 9 2.3.2 注入鎖定除頻器(ILFD) 11 2.4 高除數除頻器 13 2.4.1 電路模型簡介 13 2.4.2 鎖定頻寬分析 14 2.4.3 諧波增強技術 16 2.5 增強偶次諧波項K頻段注入鎖定除十除頻器 17 2.5.1 電路設計 17 2.5.2 實驗結果與討論 26 2.6 總結 36 第三章 使用電流再利用及諧波增強鎖定頻寬之V頻段注入鎖定除六除頻器 38 3.1 簡介 38 3.2 電流再利用(Current-Reuse)電路架構[50] 39 3.3 二次注入[53] 41 3.4 使用電流再利用及諧波增強鎖定頻寬之V頻段注入鎖定除六除頻器 47 3.4.1 電路設計 47 3.4.2 實驗結果與討論 57 3.5 總結 66 第四章 自我注入耦合考畢子四相位壓控振盪器 68 4.1 簡介 68 4.2 電路設計及分析 69 4.2.1 差動形式考畢子壓控振盪器 69 4.2.2 四相位考畢子壓控振盪器 73 4.3 實驗結果與討論 76 4.3.1 量測架設與結果 76 4.3.2 電路除錯 83 4.4 總結 90 第五章 結論 92 參考文獻 94
參考文獻	[1] B. Afshar and A. M. Niknejad, “A robust 24 mW 60 GHz receiver in 90 nm standard CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 182–183. [2] C.-H. Tseng, Y.-H. Lin, “24-GHz Self-Injection-Locked Vital-Sign Radar Sensor With CMOS Injection-Locked Frequency Divider Based on Push–Push Oscillator Topology,” IEEE Microw. Wireless Compon. Lett., vol.28, no.11, pp.1053-1055, Nov. 2018. [3] C. Li, Z. Peng, T.-Y. Huang, T. Fan, F.-K. Wang, T.-S. Horng, J.-Maria, M.-Ferreras, R. G.-Garcia, L. Ran, J. Lin, “A Review on Recent Progress of Portable Short-Range Noncontact Microwave Radar Systems,” IEEE Trans. Microw. Theory Tech. vol.65, no.5, May. 2017. [4] K. Okada et al., “A 60-GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2988–3004, Dec. 2011. [5] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang, F. Wang, and M.-C. F. Chang, “A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp.1606-1617, Jul. 2011. [6] N. Da Dalt, S. Derksen, P. Greco, C. Sandner, H. Schmid and K. Strohmayer, "A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-/spl mu/m standard digital CMOS copper technology," in IEEE Journal of Solid-State Circuits, vol. 37, no. 7, pp. 959-962, July 2002 [7] X. Zhang, X. Zhou, and A.S. Daryoush, “A theoretical and experimental study of the noise behavior of subharmonically injection locked local oscillators,” IEEE Trans. Microw. Theory Tech., vol.40, no.5, pp.895-902, May 1992. [8] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813-821, Jun. 1999. [9] Y.-H. Wong, W.-H. Lin, J.-H. Tsai, and T.-W. Huang, “A 50-to-62GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., pp.435-438, Jun. 2008. [10] K. Yamamoto and M. Fujishima, “55GHz CMOS frequency divider with 3.2GHz locking range,” in Proc. Solid-State Circuits Conf., pp. 135-138, Sept. 2004. [11] H. Wu and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 /spl mu/m CMOS frequency divider with shunt-peaking locking-range enhancement,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , pp.412-413, Feb. 2001. [12] J.-C. Chien and L.-H. Lu, “40GHz wide-locking-range regenerative frequency divider and low-phase-noise balanced VCO in 0.18μm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.544-621, Feb. 2007. [13] K.-H. Tsai, L.-C. Cho, J.-H. Wu, S.-I. Liu, “3.5mW W-band frequency divider with wide locking range in 90nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Paper, pp. 466-628, Feb. 2008. [14] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170-1174, Jul. 2004. [15] S.-L. Jang, C.-F. Lee, and W.-H. Yen, “A divide-by-3 injection locked frequency divider with single-ended input,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 2, pp. 142-144, Feb. 2008. [16] H. Wu and L. Zhang, "A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 2482-2491, Feb. 2006. [17] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu, “A wide-locking Range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 390-392, Jul. 2010. [18] X.-P. Yu, A.van Roermund, X.-L. Yan, H. M. Cheema, and R. Mahmoudi, “A 3 mW 54.6 GHz divide-by-3 injection locked frequency divider with resistive harmonic enhancement,” IEEE Microw. Wireless Compon.s Lett., vol. 19, no. 9, pp. 575-577, Sept. 2009. [19] S.-L. Jang and C.-W. Chang, “A 90 nm CMOS LC-Tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 4, pp. 229-231, Apr. 2010. [20] Y.-L. Yeh and H.-Y. Chang, “Design and analysis of a W-band divide-by-three injection-locked frequency divider using second harmonic enhancement technique,” IEEE Trans. Microw. Theory. Tech., vol. 60, no. 6, pp.1617-1625, Jun. 2012. [21] K. Yamamoto and M. Fujishima, “70GHz CMOS harmonic injection-locked divider,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 2472-2481, Feb. 2006. [22] P. Mayr, C. Weyers, and U. Langmann, “A 90GHz 65nm CMOS injection-locked frequency divider,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.198-596, Feb. 2007. [23] S.-L. Jang, C.-C. Liu, and C.-W. Chung, “A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 4, pp. 236-238, Apr. 2009. [24] S.-H. Lee, S.-L. Jang, and Y.-H. Chung, “A low voltage divide-by-4 injection locked frequency divider with quadrature outputs,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 373-375, May 2007. [25] S-L Jang, Y.-H. Chuang, S.-H. Lee, and J.-J. Chao, “Circuit techniques for CMOS divide-by-four frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 3, pp. 217-219, Mar. 2007. [26] M.-C. Chuang, J.-J. Kuo, C.-H. Wang, and H. Wang, “A 50 GHz divide-by-4 injection lock frequency divider using matching method,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 5, pp. 344-346, May 2008. [27] H.-H. Hsieh, H.-S. Chen, and L.-H. Lu, “A V-Band divide-by-4 direct injection-locked frequency divider in 0.18-µm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 2, pp. 393-405, Feb. 2011. [28] J. R. Hu and B. P. Otis, “A 3 μW, 400 MHz divide-by-5 injection-locked frequency divider with 56% lock range in 90nm CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., pp.665-668, Jun. 2008. [29] M. Li, P. Wang, T. Huang and H. Chuang, "Low-Voltage, Wide-Locking-Range, Millimeter-Wave Divide-by-5 Injection-Locked Frequency Dividers," IEEE Trans. Microw. Theory and Tech., vol. 60, no. 3, pp. 679-685, March 2012, [30] M.-W. Li, H.-C. Kuo, T.-H. Huang, and H.-R. Chuang, “60 GHz CMOS divide-by-5 injection-locked frequency divider with an open-stub-loaded floating-source injector,” IEEE RFIC Symp., Jun. 2011, pp.1-4. [31] 李銘偉，24 GHz 與60 GHz CMOS 低功耗壓控振盪器及高次諧波除頻器之毫米波射頻晶片研製，國立成功大學電腦與通信工程研究所碩士論文，民國99年。 [32] 黃致勝，微波及毫米波注入式除頻器與振盪器暨射頻前端應用，國立中央大學電機工程研究所碩士論文，民國100年。 [33] 李昇洺，V及D頻段高除數注入鎖定除頻器與四相位鎖頻迴路之研製，國立中央大學電機工程研究所碩士論文，民國106年。 [34] 詹駿清，毫米波注入鎖定振盪器及鎖頻迴路之研究，國立中央大學電機工程研究所碩士論文，民國105年。 [35] M. Acar, D. Leenaerts, and B. Nauta, “A wide-band CMOS injection-locked frequency divider,” in IEEE Microw. Wireless Compon. Lett., Jun. 2004, pp. 211-214. [36] F.-H. Huang, D.-M. Lin, H.-P. Wang, W.-Y. Chiu, and Y.-J. Chan, “20 GHz CMOS injection-locked frequency divider with variable division ratio,” in 2005 IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2005, pp. 469–472. [37] P.-H. Feng and S.-H. Liu, “A Current-reused injection-locked frequency multiplication/division circuit in 40 nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1523–1532, Apr. 2013. [38] Kuan-Hsiu Chien, Jian-Ying Chen, and Hwann-Kaeo Chiou, “Designs of K-Band Divide-by-2 and Divide-by-3 Injection-Locked Frequency Divider with Darlington topology,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 9, pp. 2877-2888, Sep. 2015. [39] Wen-Cheng Lai, Sheng-Lyqng Jang, and Guan-Zhang Li, “High-modulus Injection-Locked Frequency Divider Using Multi-Resonance Tank,” 2019 IEEE MTT-S International Microwave Symposium(IMS) Tt3D-6. [40] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18-µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594-601, Apr. 2004. [41] B. Razavi, RF Microelectronics, Prentice-Hall, 1998 [42] 劉深淵、楊清淵，鎖相迴路，滄海書局，民國100年。 [43] A. E. Sieman, Lasers, CA: University Science Books, 1986. [44] R. R. Ward, The living Clocks, New York: Alfred Knopf, 1971. [45] B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004. [46] B. Razavi, Design of analog CMOS integrated circuits, New York: McGraw-Jill, 2001, ch.2. [47] U. Singh and M. M. Green, “High-frequency CML clock divider in 0.13-µm CMOS operating up to 38 GHz,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1658-1661, Aug. 2005. [48] B. Hong and A. Hajimiri, “A General Theory of Injection Locking and Pulling in Electrical Oscillators—Part I: Time-Synchronous Modeling and Injection Waveform Design,” IEEE J. Solid-State Circuits, vol. 54 no. 8, pp. 2109-2121, Aug. 2019 [49] B. Hong and A. Hajimiri, “A General Theory of Injection Locking and Pulling in Electrical Oscillators—Part II: Amplitude Modulation in LC Oscillators, Transient Behavior, and Frequency Division,” IEEE J. Solid-State Circuits, vol. 54 no. 8, pp. 2122-2138, Aug. 2019 [50] S.-J. Yun, S.-B. Shin, H.-C. Choi, S.-G. Lee, “A 1mW Current-Reuse CMOS Differential LC-VCO with Low Phase Noise,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol.1, pp.540-616, Feb. 2005. [51] 葉彥良，應用於微波及毫米波鎖相迴路之金氧半場效電晶體注入鎖定振盪器研究，國立中央大學電機工程研究所博士論文，民國102年。 [52] 葉瀚濃，使用注入鎖定技術之W頻段除三除頻器與V頻段除六除頻器及Q頻段鎖頻迴路，國立中央大學電機工程研究所碩士論文，民國107年。 [53] M. Abdulaziz, T. Forsberg, M. Törmänen, H. Sjöland, “A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS” IEEE Trans. Microw. Theory Techn., vol.67, pp1588-1600, Apr. 2019. [54] A. Hajimiri et al., “Design Issues in CMOS Differential LC Oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May, 1999. [55] M. Li, P. Wang, et al, “Low-voltage, Wide-locking-range, Millimeter-Wave Divide-by-5 Injection-Locked Frequency Dividers,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 3, pp. 679–685, Mar. 2012 [56] J. Sun, C.-C. Boon, F. Meng, X. Yi, and W.-M. Lim, ”A V-Band CMOS Divider-by-Three ILFD With Frequency-Dependent Injection Enhancement,” IEEE Microw. and Wireless Compon. Lett., vol. 25, no. 11, pp.727-729, Nov. 2015. [57] H. Nam, J-D. Park, “A W-band divide-by-three injection-locked frequency divider with injection current boosting utilizing inductive feedback in 65-nm CMOS,” IEEE Microw. and Wireless Compon. Lett., vol. 30, no. 5, pp.516-519, May 2020. [58] M. Farazian, P.-S. Gudem, and L.-E. Larson, “A CMOS multi-phase injection-locked frequency divider for V-band operation,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 4, pp. 239–241, Apr. 2009. [59] 廖彥涵，微波與毫米波寬頻振盪器與鎖相迴路之研製，國立中央大學電機工程研究所碩士論文，民國102年。 [60] 邱垣達，低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究，國立中央大學電機工程研究所碩士論文，民國106年。 [61] H.-Y. Chang, C.-H. Lin, Y.-C. Liu, Y.-L. Yeh, K. Chen, S.-H. Wu, “65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator,” IEEE Trans. Microw. Theory Techn., vol.61, no.6, pp.2402-2413, Jun. 2013. [62] U. Decanis, A. Ghilioni, E. Monaco, A. Mazzanti, F. Svelto, “A mm-Wave quadrature VCO based on magnetically coupled resonators,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.280-282, Feb. 2011. [63] X. Ding, H. Yu, Z. Xu, Q.-J. Gu, “A Superharmonic Injection based G-band Quadrature VCO in CMOS,” IEEE International Microwave Symposium (IMS), pp345-348, Aug.2020 [64] H. Yang, R. Zhang, C. Shi, G. Chen, “An 88.68% Tuning Range Enhancement and High Process Compatibility MM-Wave QVCO with SCHI Achieving −196.6 FOMT,” IEEE Asia-Pacific Microwave Conference, pp.950-952, Jan. 2019. [65] N.-C. Kuo, J.-C. Chien, A.-M. Niknejad, “Design and Analysis on Bidirectionally and Passively Coupled QVCO With Nonlinear Coupler,” IEEE Trans. Microw. Theory Techn., vol.63, no.4, pp.1130-1141, Apr. 2015. [66] M.-T. Amin, P.-I. Mak, R.-P. Martins, “A 0.137 mm2 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol.24, no.10, pp.716-718, Oct. 2014 [67] J.-A. Hou, Y.-H. Wang, “A 7.9 GHz Low-Power PMOS Colpitts VCO Using the Gate Inductive Feedback,” IEEE Microw. Wireless Compon. Lett., vol.20, no.4, pp.223-225, Apr.2010. [68] Y. Hu, X. Chen, T. Sirburanon, J. Du, Z. Gao, V. Govindaraj, A. Zhu, R.-B. Staszewski, “17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.276-278, Feb. 2020. [69] L. Zhang, A. Ameri, Y.-A. Li, N.-C. Kuo, M. Anwar, A.-M. Niknejad, “A 37.5-45. lGHz Superharmonic-Coupled QVCO with Tunable Phase Accuracy in 28nm Bulk CMOS,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, pp.223-226, Nov. 2018. [70] M. Jalalifar, G.-S. Byun, “A Current-Reused Back-Gate Coupling QVCO Using Transformer Feedback Structure,” IEEE Microw. Wireless Compon. Lett., vol.26, no.7, pp.534-536, Jul. 2016. [71] S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, J. Choi, “A Low-Integrated-Phase-Noise 27–30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers,” IEEE J. Solid-State Circuits, vol.53, no.2, pp.375-388, Feb. 2018. [72] I.-S. Shen, C.-F. Jou, “A X -Band Capacitor-Coupled QVCO Using Sinusoidal Current Bias Technique,” IEEE Trans. Microw. Theory Techn., vol.60, no.2, pp.318-328, Feb. 2012. [73] A. Garghetti, A. L. Lacaita, S. Levantino, “A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique,” IEEE International Symposium on Circuit and Systems, pp.1-4, 2018. [74] T. Siriburanon, Satoshi, Kondo, M. Katsuragi, H. L. Liu, K. Kimura, W. Deng, K. Okada, A. Matsuzawa, “A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad,” IEEE J. Solid-State Circuits, vol.51, no.5, pp.1246-1260, May. 2016. [75] B.-E. Seow, T.-H. Huang, C.-Y. Wu, P.-Y. Pao, H.-R. Chuang, “A Low-Voltage 30-GHz CMOS Divide-by-Three ILFD With Injection-Switched Cross-Coupled Pair Technique,” IEEE Trans. Microw. Theory Techn. vol.65, no.5, pp.1560-1568, May. 2017. [76] Q. Zou, K. Ma, K. S. Yeo, “A V-Band Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider,” IEEE Microw. Wireless Compon. Lett., vol.28, no.11, pp.1020-1022, Nov. 2018. [77] W.-C. Lai, S.-L. Jang, J.-W. Jhuang, “An Injection-Locked Frequency Divider by Three with Switching Cross-couple Architecture,” IEEE International Symposium on Radio-Frequency Integration Technology, pp.159-160, Sept. 2017. [78] J. Zhang, Y. Cheng, C. Zhao, Y. Wu, K. Kang, “Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators,” IEEE J. Solid-State Circuits, vol.53, no.8, pp.2177-2189, Aug. 2018. [79] Y.-H. Lin, H. Wang, “Design and Analysis of W-Band Injection-Locked Frequency Divider Using Split Transformer-Coupled Oscillator Technique,” IEEE Trans. Microw. Theory Tech., vol.66, no.1, pp.177-186, Jan. 2018. [80] J.-H. Cheng, J.-H. Tsai, T.-W. Huang, “Design of a 90.9% Locking Range Injection-Locked Frequency Divider With Device Ratio Optimization in 90-nm CMOS,” IEEE Trans. Microw. Theory Tech. vol.65, no.1, Jan. 2017. [81] K.-H. Chien, J.-Y. Chen, H.-K. Chiou, “Designs of K-Band Divide-by-2 and Divide-by-3 Injection-Locked Frequency Divider With Darlington Topology,” IEEE Trans. Microw. Theory Tech. vol.63, no.9, pp.2877-2888, Sept. 2015. [82] S.-L. Jang, W.-C. Lai, Y.-L. Ciou, J. C. Hou, J.-W. Syu, “Divide-by-2 Injection-Locked Frequency Dividers Using the Electric-Field Coupling Dual-Resonance Resonator,” IEEE Trans. Microw. Theory Tech. vol.68, no.3, pp.844-853, Mar. 2020. [83] K.-I Oh, G. S. Kim, J.-G. Park, G.-H. Ko, D. Baek, “Fourth-order Resonator based Current Reuse Injection-Locking Frequency Divider with Peaking Inductor,” IEEE Asia-Pacific Microwave Conference, pp.1219-1219, Dec. 2019 [84] S.-L. Jang, W.-C. Lai, G.-Z. Li, Y.-W. Chen, “High Even-Modulus Injection-Locked Frequency Dividers,” IEEE Trans. Microw. Theory Tech., vol.67, no.12, pp.5069-5079 Dec. 2019. [85] S. Liu, Y. Zheng, W. M. Lim, W. Yang, “Ring Oscillator Based Injection Locked Frequency Divider Using Dual Injection Paths,” IEEE Microw. Wireless Compon. Lett., vol.25, no.5, pp.322-324, May. 2015. [86] S.-L. Jang, S.-J. Jian, C.-W. Hsue, “Wideband Divide-by-4 Injection-Locked Frequency Divider Using Harmonic Mixer,” IEEE Microw. Wireless Compon. Lett., vol.27, no.10, pp.924-926, Oct. 2017. [87] S.-L, Jang, G.-Z. Li, W.-C. Lai, “Wide-Locking Range RLC-Tank Balanced-Injection Divide-by-5 Injection-Locked Frequency Based on Harmonic Mixing,” IEEE Trans. Microw. Theory Tech., vol.68. no3. pp.894-903, Mar. 2020. [88] Q. Zou, K. Ma, K. S. Yeo, “A V -Band Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider,” IEEE Microw. Wireless Compon. Lett., vol.28, no.11, pp.1020-1022, Nov. 2018 [89] H. Zhang and Q. Xue, "Design of Wideband Low Phase Noise Class-C QVCO With Low Amplitude and Phase Errors," in IEEE Microwave and Wireless Components Letters, vol. 25, no. 11, pp. 724-726, Nov. 2015 [90] X. Yi, C. C. Boon, H. Liu, J. F. Lin and W. M. Lim, "A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 49, no. 2, pp. 347-359, Feb. 2014
指導教授	張鴻埜(Hong-Yeh Chang)	審核日期	2021-9-9
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare