金屬-絕緣層-p 型氮化鎵增強型高電子遷移率電晶 體之研究

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張懷言(Huai-Yen Chang) 查詢紙本館藏

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電機工程學系

論文名稱

金屬-絕緣層-p 型氮化鎵增強型高電子遷移率電晶體之研究
(Investigation of Metal-Insulator-p GaN EnhancementMode High Electron Mobility Transistors)

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摘要(中)

本研究針對金屬/絕緣層/p 型氮化鎵增強型高電子遷移率電晶體結構，使用三種不同絕緣層和Sample A的金屬/p 型氮化鎵增強型高電子遷移率電晶體比較，絕緣層分別是Sample B的氧化鋁、Sample C的氧化鉿加氧化鋁和Sample D的氧化鋯加氧化鋁，探討其元件特性之差異及其可能之原因。元件直流特性方面，相較於金屬/p 型氮化鎵元件的臨界電壓為 0.6 V，三種金屬/絕緣層/p 型氮化鎵元件的臨界電壓均為 0.9 V，主要是因為當元件的閘極施加正偏壓時，會有壓降在絕緣層產生，需要施加更大的柵極電壓才能使通道導通，可是加入絕緣層使閘極電容降低，也犧牲了元件在閘極電壓為 6 V時的飽和電流。此外，Sample A、Sample B、Sample C和Sample D的閘極崩潰電壓則分別為10.6 V、14 V、13.4 V、12.9 V，顯示絕緣層的存在降低了電洞在閘極端的穿隧行為，進而抑制閘極端崩潰。在元件的動態特性方面，使用不同偏壓下的脈衝量測，發現沉積絕緣層引起了更嚴重的臨界電壓偏移。雙向和變頻的 C-V 量測除了觀察遲滯效應的存在，也估算了元件的界面能態密度，Sample A 的界面能態密度為 7.9 × 1011eV-1；Sample B
為 2.8 × 1012eV-1；Sample C 為 3.1 × 1012cm-2eV-1；Sample D 為 3.2 × 1012cm-2eV-1，可以發現當沉積絕緣層時界面能態密度的增加。

摘要(英)

This research is aimed at metal/insulator/p-GaN gate enhancement-mode high electron mobility transistors (HEMTs) to reduce gate leakage current at high gate bias conditions. In this work, a Schottky p-GaN gate HEMT (Sample A) was fabricated as the reference. HEMTs with three different gate insulators, i.e. Al2O3 (Sample B), HfOx+Al2O3 (Sample C), and ZrO2+Al2O3 (Sample D), were investigated and compared. Possible reasons for the different characteristics between these samples were also given.
Compared with the metal/p-GaN device (Sample A), which has a threshold voltage of 0.6 V, the three metal/insulator/p-GaN devices (Sample B, C, and D) exhibit the same threshold voltage of 0.9 V. This is attributed to the additional voltage drop on the insulator layer, and a larger gate voltage is needed to turn on the channel. However, adding an insulator layer to the p-GaN layer results in the reduction of gate capacitance, and thus the saturation current at a gate voltage of 6 V. In addition, while the gate breakdown voltage of the metal/p-GaN device is 10.6 V, those of the devices with Al2O3, HfOx+Al2O3, and ZrO2+Al2O3 insulators are 14 V, 13.4 V, and 12.9 V, respectively. This shows that the insulator layer effectively reduces the tunneling of holes at the gate terminal, thereby preventing the gate terminal from collapsing. The dynamic characteristics of the devices evaluated by pulsed measurements under different bias voltages indicated that the deposition of the insulator layer causes a more significant threshold voltage shift. The bidirectional sweep and variable frequency capacitance-voltage measurements show the existence of the hysteresis effect, which are used to estimate the interface state density. The interface state density of Sample A, B, C, and D is 7.9×1011 cm-2 eV-1, 2.8×1012 cm-2 eV-1, 3.1×1012 cm-2 eV-1, and 3.2×1012 cm-2 eV-1, respectively. This work shows that adding an insulator to the p-GaN gate increases the threshold voltage and breakdown voltage at the expenses of drain current and threshold voltage shift.

關鍵字(中)

★ 氮化鎵
★ 絕緣層
★ p 型氮化鎵
★ 氧化鋁
★ 氧化鉿加氧化鋁
★ 氧化鋯加氧化鋁

關鍵字(英)

論文目次

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 viiii
表目錄 ix
第一章緒論 1
1.1 前言 1
1.2 氮化鎵材料與元件概述 3
1.2.1 氮化鎵極化效應 3
1.2.2 增強型氮化鋁鎵/氮化鎵高電子遷移率電晶體 5
1.3 研究動機與論文架構 11
第二章元件製程 12
2.1 前言 12
2.2 儀器介紹 12
2.3 元件製程流程 14
第三章元件特性分析 20
3.1 前言 20
3.2 能帶模擬分析 20
3.3 直流特性分析 25
3.4 崩潰特性分析 28
3.5 動態特性分析 31
3.6 C-V特性分析 39
3.7 結論 44
第四章　結論與未來展望 45
參考文獻 46

參考文獻

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指導教授

綦振瀛(Jen-Inn Chyi)

審核日期

2021-9-23

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