基於靜態隨機存取記憶體的內存計算記憶體測試

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蔡采玲(Tsai-Ling Tsai) 查詢紙本館藏

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電機工程學系

論文名稱

基於靜態隨機存取記憶體的內存計算記憶體測試
(Testing of SRAM-Based In-Memory-Computing Memories)

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至系統瀏覽論文 (2026-10-6以後開放)

摘要(中)

大多現代計算機系統是建立在馮紐曼(von Neumann)架構上，也就是架構上記憶體及處理器是分開來的，當資料在這兩者之間做搬移時，會造成能量的耗損以及遭遇表現上的限制，尤其是面對需要大量資料處理的應用，內存計算(CIM)是一種為解決這種瓶頸而提出的解決方式，CIM記憶體有記憶體模式與計算(computing)模式。現今已有多種靜態隨機存取記憶體(SRAM)單元(cell)及SRAM的模型用來實現CIM。這使得測試CIM記憶體比測試傳統記憶體更為困難。在此篇論文我們提出一個測試CIM SRAM的方法，包括比較缺陷(defect)導致的故障(fault)模型，還有如何發展測試演算法。一開始我們會先介紹CIM SRAMs在記憶體模式與計算模式中建立故障模型的方式，接著比較缺陷在這兩種模式導致的故障模型，最後介紹如何發展CIM SRAM的測試演算法。我們所提出的方法會使用8T及10T SRAM單元作個案討論。具有8T和10T SRAM單元的CIM SRAM的故障是透過注入電氣缺陷來定義的，接著比較在記憶體模式和計算模式中發生的故障模型，最後針對記憶體模式與計算模式的故障分別開發了測試演算法。

摘要(英)

Most modern computer systems are based on von Neumann architecture, which separates the memory and the processor. The data movement between the memory and the processor
limits the performance and power consuming, especially for data-intensive applications. Computing-In-Memory (CIM) architecture is one possible approach to cope with the bottleneck. A CIM memory can be operated in memory mode or computing mode. Also, various memory cells were proposed to realize CIM memories. Those make the testing of CIM memories
to be more difficult than that of conventional memories. In this thesis, we propose a test methodology for CIM SRAMs, including fault modeling, fault collapsing by defects, and
test development. A fault modeling method of CIM SRAMs in memory mode and computing mode is introduced first. Subsequently, faults in memory mode and computing mode are collapsed by defects. Then, a test development method for CIM SRAMs is introduced. The proposed test methodology applied to CIM SRAMs with 8T and 10T SRAM cells are presented as case studies. Faults of the CIM SRAMs with 8T and 10T SRAM cells are defined by injecting electrical defects. Then, faults occur in both memory mode and computing mode are collapsed by defects. Finally, test algorithms are developed for the faults in memory mode and computing mode.

關鍵字(中)

★ 靜態隨機存取記憶體
★ 記憶體測試
★ 錯誤模型

關鍵字(英)

★ SRAM
★ memory testing
★ computing-in-memory
★ CIM
★ Fault model

論文目次

1 Introduction 1
1.1 Computing In Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 SRAM-Based CIM Memories . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Test Methodology for SRAM-based CIM Memories 7
2.1 CIM SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Digital CIM SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Analog CIM SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 SPICE Model Building . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 Fault Analysis of Memory Array . . . . . . . . . . . . . . . . . . . . . 17
2.3 Fault Collapsing By Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Test Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 Test for Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.2 Test for Peripheral Circuit . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Case Study: Testing of CIM SRAMs with 10T and 8T Cells 25
3.1 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 SPICE Model Building . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2 Defect Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1.3 Flow of the Fault Analysis . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.4 Fault Analysis in Memory Mode . . . . . . . . . . . . . . . . . . . . . 31
3.1.5 Fault Analysis in Computing Mode . . . . . . . . . . . . . . . . . . . 35
3.2 Defined Faults and Corresponding Defects . . . . . . . . . . . . . . . . . . . 40
3.2.1 Defined Faults for 10T SRAM in Memory Mode . . . . . . . . . . . . 40
3.2.2 Defined Faults for 10T BL-Computing SRAM in Computing Mode . 41
3.2.3 Case Study: 10T SA-computing SRAM in Computing Mode . . . . . 47
3.2.4 Case Study: 8T2P CIM SRAM in Memory Mode . . . . . . . . . . . 50
3.2.5 Case Study: 8T2P CIM SRAM in Computing Mode . . . . . . . . . . 50
3.2.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3 Fault Collapsing By Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.3.1 Fault Collapsing By Defects: 10T BL-Computing SRAM . . . . . . . 61
3.3.2 Fault Collapsing By Defects: 10T SA-computing SRAM . . . . . . . 62
3.3.3 Fault Collapsing By Defects: 8T2P CIM SRAM . . . . . . . . . . . . 63
3.4 Test Algorithm Development . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Conclusion and Future Work 68

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指導教授

李進福(Jin-Fu Li)

審核日期

2021-10-12

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