| 摘要(英) |
Power networks which provide supply voltage and ground to transistors are essential for modern ICs. It is necessary to consider IR-drop when constructing power network. The IR-drop occurs during the transfer of the supply voltage from the power network to the circuit. The wires of the power network contain parasitic resistance which will lead the dropping of supply voltage. If a large amount of voltage drop occurs on the power network in a circuit, the noise margin of the circuit will be reduced, and the performance of the circuit will be degraded.
In previous researches, the researchers designed an IR-drop-friendly power network to reduce the IR-drop of the circuit. On the other hand, the wire of the power network consumes the routing resources. Moreover, the power stripes connect to the underlying circuit through the via arrays. The via arrays also occupy the routing resource, thereby increasing the complexity of the circuit routing and causing routing congestion. Therefore, it is necessary to consider the routing issue when designing the power network.
In this work, we propose a power network refinement framework which can generate appropriate power network structure for better circuit timing by considering both IR-drop and routing congestions. In our framework, we add additional power stripes based on the initial power network to improve the circuit timing. We use a cost function to analyze the relationship between circuit timing and IR-drop as well as routing congestions, and add the power stripes based on the cost function evaluation. The experiment result shows that we can improve the total negative slacks of the circuit by the 5.6% compared to the original design. Also, we can save the 36% of the IR drop compared to the original design. |
| 參考文獻 |
[1] Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "A novel framework for faster-than-at-speed delay test considering IR-drop effects." Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design. 2006.
[2] Ajami, Amir H., et al. "Analysis of IR-drop scaling with implications for deep submicron P/G network designs." Fourth International Symposium on Quality Electronic Design, 2003. Proceedings. IEEE, 2003.
[3] Bai, Geng, Sudhakar Bobba, and Ibrahim N. Hajj. "Static timing analysis including power supply noise effect on propagation delay in VLSI circuits." Proceedings of the 38th annual Design Automation Conference. 2001.
[4] Chang, Wen-Hsiang, Mango C-T. Chao, and Shi-Hao Chen. "Practical routability-driven design flow for multilayer power networks using aluminum-pad layer." IEEE Transactions on Very Large-Scale Integration (VLSI) Systems 22.5 (2013): 1069-1081.
[5] Chang, Wen-Hsiang, et al. "Generating routing-driven power distribution networks with machine-learning technique." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36.8 (2017): 1237-1250.
[6] Chang, Wen-Hsiang, et al. "Power distribution network generation for optimizing IR-drop aware timing." 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD). IEEE, 2020.
[7] Chhabria, Vidya A., et al. "Template-based PDN synthesis in floorplan and placement using classifier and CNN techniques." 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2020.
[8] Chhabria, Vidya A., and Sachin S. Sapatnekar. "OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2021).
[9] Guyon, Isabelle, et al. "Gene selection for cancer classification using support vector machines." Machine learning 46.1 (2002): 389-422.
[10] Kobayashi, Susumu, and Kenichi Horiuchi. "An LOCV-based static timing analysis considering spatial correlations of power supply variations." 2011 Design, Automation & Test in Europe. IEEE, 2011.
[11] Lin, Jai-Ming, Jhih-Sheng Syu, and I-Ru Chen. "Macro-aware row-style power delivery network design for better routability." 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2018.
[12] Liu, Sean Shih-Ying, et al. "Effective power network prototyping via statistical-based clustering and sequential linear programming." 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2013.
[13] Nithin, S. K., Gowrysankar Shanmugam, and Sreeram Chandrasekar. "Dynamic voltage (IR) drop analysis and design closure: Issues and challenges." 2010 11th International Symposium on Quality Electronic Design (ISQED). IEEE, 2010.
[14] Popovich, Mikhail, and Eby G. Friedman. "Noise aware decoupling capacitors for multi-voltage power distribution systems." Sixth international symposium on quality electronic design (isqed′05). IEEE, 2005.
[15] Popovich, Mikhail, and Eby G. Friedman. "Decoupling capacitors for multi-voltage power distribution systems." IEEE Transactions on Very Large-Scale Integration (VLSI) Systems 14.3 (2006): 217-228.
[16] Popovich, Mikhail, et al. "On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits." IEEE Transactions on Very Large-Scale Integration (VLSI) Systems 16.7 (2008): 908-921.
[17] Sato, Takashi, et al. "A time-slicing ring oscillator for capturing instantaneous delay degradation and power supply voltage drop." IEEE Custom Integrated Circuits Conference 2006. IEEE, 2006.
[18] Saxena, Jayashree, et al. "A case study of IR-drop in structured at-speed testing." International Test Conference, 2003. Proceedings. ITC 2003.. IEEE Computer Society, 2003.
[19] Saxena, Prashant, Rupesh S. Shelar, and Sachin Sapatnekar. Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer Science & Business Media, 2007.
[20] Su, Haihua, et al. "Congestion-driven codesign of power and signal networks." Proceedings 2002 Design Automation Conference (IEEE Cat. No. 02CH37324). IEEE, 2002.
[21] Sun, Zeyu, et al. "Voltage-based electromigration immortality check for general multi-branch interconnects." 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2016.
[22] Tehranipoor, Mohammad, and Kenneth M. Butler. "Power supply noise: A survey on effects and research." IEEE Design & Test of Computers 27.2 (2010): 51-67.
[23] Wei, Yaoguang, et al. "GLARE: Global and local wiring aware routability evaluation." DAC Design Automation Conference 2012. IEEE, 2012.
[24] Zhou, Han, et al. "EM-aware and lifetime-constrained optimization for multisegment power grid networks." IEEE Transactions on Very Large-Scale Integration (VLSI) Systems 27.4 (2019): 940-953. |
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