應用於藍芽系統之CMOS射頻前端電路設計

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姓名

莊家碩(Jia-Soy Chuang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於藍芽系統之CMOS射頻前端電路設計
(RF CMOS Front-End Circuit Design for Bluetooth Receiver)

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摘要(中)

在本論文中, 以應用於藍芽無線接收系統的來探討射頻前級的整合性,並且針對系統規格提出適用於藍芽系統之低中頻接收機,所有的線路包含有低雜訊放大器,混波器,鏡相消除濾波器, 及正交信號產生器, 模擬上顯示鏡相消除為30dB,
雜訊指數為15.2dB, 敏感度-70.8dBm, 電壓增益35.8dB, 三階信號交會點-14dBm. 使用3.3V的電壓, 及台灣積體電路公司所提供 0.6微米 SPTM 金氧半場效應電晶體, 功率消耗為250mW, 面積是3000微米4000微米.

摘要(英)

Since the rapid development of the CMOS technology, a RF analog front-end receiver can be integrated on a single chip. This thesis introduces a highly integrated RF receiver front end for Bluetooth system. This front-end design composed of low noise amplifier, two downconversion mixers, passive polyphase with buffers, and active polyphase filter. It receives the 2.4GHz desired high frequency signal ,and then translates it to 700KHz. Besides downconversion, it also needs image rejection by active polyphase filter. At last, it generates I_Q path and feed I_Q to baseband. Before I_Q fed into baseband, it needs AGC to reduce the dynamic range (44dB) and SAW filter as channel select filter. The design of AGC is not included in the thesis.
The whole analog front-end is implemented by using TSMC 0.6um SPTM standard CMOS technology under 3.3V power supply. It has 35.8dB cascaded gain, 15.2dB noise figure, 24dB image rejection ratio, -14dBm IIP3. The total RF front-end power consumption is about 250mW. The total chip area is .

關鍵字(中)

★ 藍芽
★ 射頻電路

關鍵字(英)

★ Bluetooth
★ RF Circuit

論文目次

Contents
1. Introduction 3
1.1 Motivations……………………………….. 3
1.2 Thesis Organization………………………. 4
2. Receiver Architectures Overview 5
2.1 Introduction………………………………... 5
2.2 General Considerations……………………. 6
2.3 Heterodyne Receiver………………………. 8
2.4 Homodyne Receiver………………………. 10
2.5 Image-Reject Receiver…………………….. 13
2.5.1 Hartley architecture …………………….. 13
2.5.2 Weaver architecture…………………….. 15
2.6 Wideband-IF Receiver…………………….. 16
2.7 Low-IF Receiver ………………………….. 17
2.8 Summary ………………………………….. 19
3.Bluetooth Architecture 21
3.1 Introduction ………………………………. 21
3.2 Specifications …………………………….. 22
3.3 Active Polyphase Receiver ………………. 24
3.3.1 Complex signal domain ………………. 24
3.3.2 Real signal domain …………………. 27
3.4 Macros specifications ……………………. 30
3.5 Summary ………………………………… 31
4.Low Noise Amplifier 33
4.1 Introduction ………………………………. 33
4.2 Integrated Inductors Realization …………. 33
4.3 Noise Figure ……………………………… 37
4.4 Circuit Design and Simulation Results …….. 39
4.5 Physical Layout …………………………….. 47
4.6 Summary …………………………………… 48
5.Mixer 49
5.1 Introduction ………………………………… 49
5.2 Circuit Design and Simulation Results …….. 49
5.2.1 Conversion gain ………………………… 51
5.2.2 Noise figure …………………………….. 51
5.2.3 Simulation results …………………….. 52
5.3 Physical Layout …………………………….. 53
5.4 Summary …………………………………… 55
6.Quadrature Generator 56
6.1 Introduction ……………………………….. 56
6.2 Polyphase Network ……………………….. 56
6.3 Buffer ……………………………………... 58
6.4 Physical Layout …………………………… 59
6.5 Summary ………………………………….. 60
7.Active Polyphase Filter 61
7.1 Introduction ………………………………... 61
7.2 Dou.ble-MOSFET Resistor ………………… 61
7.3 Operational Amplifier ……………………… 63
7.4 6th order Butterworth Filter ………………… 65
7.5 Physical Layout ……………………………. 68
7.6 Summary …………………………………… 70
8.Conclusions 71
Appendix 72

參考文獻

[1] P.R. Gray and R.G. Meyer, "Analysis and Design of Analog Integrated Circuits", 3rd Edition, John Wiley & Sons, 1993.
[2] Behazad Razavi, "RF Micorelectronics", Prentice Hall Inc., 1998.
[3] Jan Crols and Michiel Steyaert, "CMOS Wireless Transceiver Design", Kluwer Academic Pub, 1997.
[4] B. Razavi, "Challenges in Portable RF Transceiver Design, " IEEE Circuits and Devices Magazine, vol. 12, pp. 12-25, Sept. 1996
[5] P.R.Gray and R. G. Meyer, Analysis and Design of analog Integrated Circuits. New York: John-Wiley&Sons, 1993.
[6] Tang-Huei Chen, "CMOS RF Front-End Circuit Designs for Personal Handy-Phone System Application", master's thesis, National Central University, 1998.
[7] Z. Y. Chang and W. M. Sansen, Low-noise wide-band amplifier in Bipolar and CMOS technologies. Kluwer Academic, 1991
[8] C.C Su, "CMOS High Frequency Model and it's Application for RF Circuit Design," master's thesis, National Central University, 1999.
[9] P.-C. Chiu, "A 2V CMOS 900MHZ CMOS RF Front-End," Master's thesis, National Chiao-Tung University, Hsin-Chu, Taiwan, ROC, 1996.
[10] J. Yumg-Cieh Chang, "An Integrated 900MHZ Spread Spectrum Wireless Receiver in 1-um CMOS and a Suspended Inductor Technique," PHD's thesis, UCLA,1998.
[11] J.V.d.S.Suharli Tedia and H.H Williams, " Analytical and Experimental Studies of Thermal Noise in MOSFET's," IEEE Trans. On Electron Devices, vol. 41, pp. 2069-2075, Nov. 1994
[12] D.K. Shaefer and T. H. Lee, "A 1.5GHz CMOS Low Noise Amplifier," IEEE Jounal of Solid State Circuit, vol. 32, pp. 745-759, May 1997.
[13] R. Jindal, "Noise Associated with Distributed Resistance of MOSFET Gate Structure in Integrated Circuits," IEEE Trans. On Electron Devices, vol. ED-31, pp. 1505-1509, Oct. 1984.
[14] R.-H. Y. Behzad Razavi and K. F. Lee, "Impact of Distributed Gate Resistance on the Performance of MOS Devices," IEEE Transaction on Circuit and Systems-I: Fundamental Theorey and Applications, vol. 41, pp. 750-754, Nov. 1994.
[15] A. Rofougaran, J. Y. C. Chang, maryam Rofougaran, and A. A. Abisi, "A 1GHz CMOS RF Front-End IC for a Direct Conversion Wireless Receiver", IEEE Journal of Solid State Circuits, vol. 31, pp. 880-889, July 1996.
[16] J.Crols and Michiel S.J. Steyaert, "A 1.5GHz Highly Linear CMOS Downconverson Mixer", IEEE Journal of Solid State Circuits, vol. 30, pp. 736-742, July 1995.
[17] J. C. Rudell and P. R. Gray, "CMOS VLSI Frequency Translation for Multi-Standard Wireless Communication Transceivers", Presentation Slides, Apr. 1996.
[18] Y. Lu , "A 2V CMOS RF Front-End Design for WLAN application", master's thesis, National Central University, 1997.
[19] C.S. Wang, "A 2V CMOS RF Front-End Design for 900MHz DECT application", master's thesis, National Central University, 1999.
[20] Mark D. McDonald, "A 2.5GHz BiCMOS Image-Reject Front-End, "ISSCC Digest of Technical Papers, 1993.
[21] Richard G.Beale, "A NEW MOSFET-C Universal Filter Structure for VLSI", IEEE Journal of Solid State Circuits, vol. 23, no. 1, February 1988.
[22] Jacques C.Rudell, Jeffrey A.Weldon, Jia-Jiunn Ou, Li Lin, and P.R. Gray, "An Integrated GSM/DECT Receiver: Design Specifications", UCB Electronics Research Laboratory Memorandum, 1997.
[23] B. K. Ko and K. Lee, "A Comparative Study on the Various Monolithic Low Noise Amplifier Circuit Topologies for RF and Microwave Application," IEEE Journal of Solid State Circuit, vol. 31, pp. 1220-1225, Aug. 1996.
[24] T. H. Lee, "CMOS LNA Design," ISSCC Short Course, 1997
[25] J.J.Ou and Paul R.Gray, "CMOS Low Noise Amplifier Design for monolithic RF Modems," ISSCC Presentation Slides, May 1996.
[26] J.J.Ou and Paul R.Gray el. Etc, "An effective Gate Resistance Model for CMOS RF and Noise Modeling", Dec. 1998.
[27] Jacques C. Rudell, Jia-jiunn Ou, T. B. Cho, George Chien, and P.R. Gray, "A 1.9GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications", IEEE Journal of Solide State Circuits, vol. 32, no.12, December 1997.
[28] Young J.Shin and Klass Bult, "An Inductorless 900MHZ RF Low-Noise Amplifier in 0.9umCMOS," IEEE CICC, pp. 513-516, 1997
[29] Wiliam B. Kuhn and Naveen K. Yanduru, "Spiral Inductor Substrate Loss Modeling In Silicon RFICs," Microwave Journal, pp. 66-81, March 1999.
[30] W.B. Kuhn, A. E.-Riad, and F.W. Stephenson, "Centre-Tapped Spiral Inductors for Monolithic Bandpass Filters," Electronics Letters, vol. 31, pp. 625-626, Apr. 1995.
[31] J. N. Burghartz, M. douyer, and K. A. Jenkins, "Microwave Inductors and Capacitors in Standard Multilevel Interconnect Silicon Technology," IEEE Trans. Microwave Theory and Techniques, vol. 44, pp. 100-104, Jan. 1996.
[32] M. Souyer, J. N. Burghartz, K. A. Jenkins, S. Ponnapalli, J.F. Ewen, and W.E, Pence, "Multilevel monothic inductors in silicon technology," Electronics Letters, vol. 31, pp. 359-360, Mar. 1995.
[33] F.W.S. William B. Khun and A. Elshabini-Riad, "A 200MHz CMOS Q-enhanced LC Bandpass Filter", IEEE Journal of Solid State Circuits, vol. 31, pp. 1112-1121, Aug. 1996.

指導教授

周世傑(Shyh-Jye Jou)

審核日期

2000-7-18

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