TrustFURE: 軟體定義衛星之防竄改系統

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姓名

盧俊安(Chun-An Lu) 查詢紙本館藏

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軟體工程研究所

論文名稱

TrustFURE: 軟體定義衛星之防竄改系統
(TrustFURE: A Tamper Resistance System for Software Defined Satellite)

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摘要(中)

軟體定義衛星透過更新FPGA韌體執行不同的衛星任務。為了遠端更新的安全性，我們提出了軟體定義衛星的防竄改系統TrustFURE。現有的更新方案致力於可恢復性、動態更新和傳輸安全，但是對韌體的攻擊缺乏考量。 TrustFURE禁用豐富執行環境（REE）中的FPGA配置介面。 TrustFURE還在可信執行環境（TEE）中實現用於FPGA更新的可信應用程式和安全驅動程式，以防止攻擊者竄改或竊取韌體。此外，為了使衛星運作可靠，TrustFURE還整合故障恢復機制，使衛星能夠自我檢測故障並恢復正常運作。最後，我們在Xilinx的ARM/FPGA系統晶片開發板上實驗並分析了我們的實作，證明了它的安全性、可靠性和低開銷。

摘要(英)

Software defined satellites perform different space missions by updating the FPGA firmware. To perform the secure remote update, we propose TrustFURE, a tamper resistance system on software defined satellite. Existing update schemes are dedicated to recoverability, dynamic updates and transport security, but they do not consider attacks on the firmware. TrustFURE disables the FPGA configuration interface in Rich Execution Environment (REE). TrustFURE also includes trusted applications and security drivers for FPGA updates, which are implemented in Trusted Execution Environment (TEE) to prevent attackers from tampering with or stealing firmware. In addition, to make the satellite operation reliable, TrustFURE also integrates failure recovery mechanism, so that the satellite can detect its failure and return to normal operation. Finally, we evaluated our implementation on Xilinx ARM/FPGA SoC development board, illustrating its security, reliability and low overhead.

關鍵字(中)

★ FPGA更新
★ 故障恢復
★ 軟體定義衛星
★ 可信執行環境
★ ARM TrustZone

關鍵字(英)

★ FPGA Update
★ Failure Recovery
★ Software Defined Satellite
★ Trusted Execution Environment
★ ARM TrustZone

論文目次

中文摘要 i
Abstract ii
致謝 iii
Contents iv
List of Figures viii
List of Tables ix
1 Introduction 1
2 Related Works and Preliminary 4
2.1 Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Trusted Execution Environment . . . . . . . . . . . . . . . . . . 4
2.1.2 ARM TrustZone . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.3 Zynq UltraScale+ Architecture . . . . . . . . . . . . . . . . . . . 7
2.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 Firmware Update Mechanism . . . . . . . . . . . . . . . . . . . 9
2.2.2 PL Firmware Update Mechanism . . . . . . . . . . . . . . . . . 10
2.2.3 MPSoC (ARM Processor + FPGA) Risk Analysis . . . . . . . . . 12
3 System Model 14
3.1 Satellite Firmware Update System . . . . . . . . . . . . . . . . . . . . . 14
3.2 System Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Threat Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Physical factor . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2 Personal factor . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Secure PL Firmware Update Design 19
4.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Restricting Configuration Interfaces . . . . . . . . . . . . . . . . . . . . 20
4.2.1 Disable access to sensitive PM services . . . . . . . . . . . . . . 21
4.2.2 Disable PL configuration from Normal World by removing Xilfpga library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Normal World . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.1 Remove FPGA Manager Driver and FPGA Utility . . . . . . . . 22
4.3.2 Trigger PL update . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Secure World . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1 PL Updater Trusted Application . . . . . . . . . . . . . . . . . . 23
4.4.2 Bitstream Downloader . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.3 PL Manager Pseudo Trusted Application . . . . . . . . . . . . . 23
4.4.4 Secure Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 TrustFURE Data and Control Flow . . . . . . . . . . . . . . . . . . . . . 24
5 Secure PL Firmware Update Implementation 27
5.1 Custom PMU firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 PL Updater Trusted Application . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1 Detail of secure memory . . . . . . . . . . . . . . . . . . . . . . 29
5.2.2 Detail of OP-TEE page tables . . . . . . . . . . . . . . . . . . . 29
5.2.3 Details of Performance Optimization . . . . . . . . . . . . . . . 30
5.3 Bitstream Downloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4 PL Manager PTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5 PCAP Secure Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.1 Pre-processing of PL firmware . . . . . . . . . . . . . . . . . . . 32
5.6 DMA Secure Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6.1 Detail of cache coherence . . . . . . . . . . . . . . . . . . . . . 33
6 Automatic Failure Recovery Mechanism 35
6.1 Application Layer Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 System and Hardware Layer Failure . . . . . . . . . . . . . . . . . . . . 37
6.2.1 System Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . 39
7 Evaluation 40
7.1 Security Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1.1 PL Configuration Interfaces . . . . . . . . . . . . . . . . . . . . 40
7.1.2 PL Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1.3 Trust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1.4 Trusted Computing Base . . . . . . . . . . . . . . . . . . . . . . 42
7.1.5 Minimize modification . . . . . . . . . . . . . . . . . . . . . . . 43
7.1.6 Side Channel Attacks on DDR Memory . . . . . . . . . . . . . . 43
7.2 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.1 Invoke Execution Time . . . . . . . . . . . . . . . . . . . . . . . 43
7.2.2 Execution Time of PL Update . . . . . . . . . . . . . . . . . . . 44
7.2.3 Compare Update Speed with Xilinx Solution . . . . . . . . . . . 44
7.3 Analysis of Failure Recovery . . . . . . . . . . . . . . . . . . . . . . . . 46
8 Conclusion 47
Bibliography 48
Appendices 56
A Remove PMU firmware from Xilfpga . . . . . . . . . . . . . . . . . . . 57
B Bitstream Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
C Parallelized startup of systemd . . . . . . . . . . . . . . . . . . . . . . . 60
D System Watchdog Timer (SWDT) . . . . . . . . . . . . . . . . . . . . . 60
E PMU handling of timeout signals and robustness . . . . . . . . . . . . . 61

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指導教授

張貴雲(Guey-Yun Chang)

審核日期

2022-9-7

推文