| 摘要(英) |
In this paper, we propose a model of a feature extraction method to recognize grid failure pattern in wafer map. The actual wafer we use is the WM-811K wafer database provided by TSMC, and the failure patterns can be divided into the following nine categories: Center, Donut, Scratch, Edge-Ring, Edge-Loc, Loc, Near-Full , Random, None. The grid failure pattern discussed in this paper is not classified as above, and the hidden grid failure pattern is difficult to be recognized by human observation. Therefore, this paper uses two methods to label grid failure pattern. The first method is directly label by human observation. In the second method, we use program to collect possible hidden grid failure pattern, and then label grid failure pattern by human observation.
In the first step of the model, we use the DBSCAN algorithm to remove the clusters; Secondly, we found that the line defect points will not be filtered out in the first step, and will cause misjudgment of the grid failure pattern recognition, so in the second step of the model, we remove the line defect points; Then, in the third step of the model, we need to find the grid failure pattern on the wafer map. We classify the grid failure pattern into three types: column, row and checkerboard according to the repeated direction. Search for continuous bad dies in both row and column directions, and then speculate whether there is checkerboard type grid failure pattern. After obtaining the number of grid failure pattern of column type, row type and checkerboard type, three judgments are made way to recognize grid failure pattern.
Finally, we analyze the results of recognition model, and use the F1-Score as the judgment indicator for model improvement. The final version of the grid failure pattern recognition model, the F1-Score is 74.40%, and the simulation time is about 40.07 ms/wafer. |
| 參考文獻 |
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[6] N. Yu, Q. Xu and H. Wang, "Wafer Defect Pattern Recognition and Analysis Based on Convolutional Neural Network," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 566-573, Nov. 2019, doi: 10.1109/TSM.2019.2937793.
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[8] C. H. Jin, H. J. Na, M. Piao, G. Pok and K. H. Ryu, "A Novel DBSCAN-Based Defect Pattern Detection and Classification Framework for Wafer Bin Map," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 3, pp. 286-292, Aug. 2019, doi: 10.1109/TSM.2019.2916835. |
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