| 摘要(英) |
In this paper, we discuss two parts. First, we focus multivariate analysis of wafer maps. Second part is model analysis and the results of experiment. In this research, we should know yield, B-score and similarity according to previous research. Then, we use above three variables to do multivariate analysis. Last but not least, we use K-medoids cluster to grouping the data what we get in previous analysis.
Second part, we use first part steps to test synthetic wafer maps. We use synthetic wafer maps which are symptomatic, including Center, Donut, Scratch, Edge-Ring, Edge-Loc and Loc. Each failure type wafer maps are produced in different yields and die sizes respectively.
Finally, we apply our experiment steps to real world wafer maps which are produced by TSMC WM-811K database which is contained labeled wafer map lots in 172K. We discuss the situations in real world wafer maps. |
| 參考文獻 |
[1] Ming-Ju Wu, Jyh-Shing Roger Jang, and Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[2] Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation”, Asian Test Symposium (ATS′96), pp.258-260, Nov. 1996.
[3] Takeshi Nakazawa, and Deepak V. Kulkarni, “Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network”, IEEE Transaction on Semiconductor Manufacturing, Vol 31, pp. 309-314, May. 2018.
[4] Jwu E Chen, Tung-Ying Lu, and Hsing-Chung Liang, “Testing the Spatial Pattern Randomness on Wafer Maps”, VLSI Test Technology Workshop (VTTW), Jul. 2019.
[5] Cheng-Yan Wu, “Applications of Yield and Randomness Homogeneity Tests to Wafer Map Analysis”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Jan. 2020.
[6] Ming-Ju Wu, Jyh-Shing R. Jang, Jui-Long Chen, “Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets”, IEEE Transactions on Semiconductor Manufacturing, Vol 28, pp. 1-12, Feb. 2015.
[7] Ya-Hsuan Wu, “Wafer Map Partition Analysis to Enhance Systematic Error Resolution”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Apr. 2018.
[8] Tung-Ying Lu, “Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification”, M.S. thesis, Dept. Electron. Eng., National Central University, Taoyuan, Taiwan (R.O.C.), Oct. 2019.
[9] T. Hsieh, C. Liao, Y. Huang and C. Chien, "A new morphology-based approach for similarity searching on wafer bin maps in semiconductor manufacturing," Proceedings of the 2012 IEEE 16th International Conference on Computer Supported Cooperative Work in Design (CSCWD), Wuhan, 2012, pp. 869-874, doi: 10.1109/CSCWD.2012.6221923.
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[10] 林敬儒林敬儒,“Identification of the Classifier for the Pattern of Spatial Randomness”, 碩士論文﹐中央大學﹐2018. |
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