| 摘要(英) |
With the evolution of technology nodes and the improvement of process technology, transistors and metal wires can be scaled down, more transistors can be accommodated in a unit area. However, as the area is reduced, the degree of metal wire routing will become more and more complicated. Since the length of the interconnect metal is increased, the resistance value of the metal wire is increased. On the other hand, the smaller the distance between the metal wires, the metal to metal coupling cannot be ignored. Therefore, this thesis uses the monolithic 3D stacking technology to optimize the circuit characteristics considering different 3D stacking designs.
The logic circuits discussed in this thesis includes Inverter, NAND and NOR. We analyze the characteristics of the logic circuit by using Sentaurus Structure Editor (SDE) from Synopsys TCAD to build a three-dimensional structure. In the first part, we introduce the device structure, fin field effect transistor (FinFET), and the metal wire structure parameters of middle-of-line (MOL) and back-end-of-line (BEOL). In the second part, we use the Transistor-Level monolithic 3D stacking technique to design logic circuits, this thesis investigated three Transistor-Level monolithic 3D stacking schemes, including Folding, Stitching and Separating. All the Transistor-Level monolithic 3D stacking schemes in this thesis are designed with N-type transistors on the top-tier and P-type transistors on the bottom-tier. The purpose is to adjust the manufacturing process and optimize the transistor characteristics independently.
In the third part, we analyze the logic circuits of Transistor-Level monolithic 3D stacking schemes compared with traditional 2D stacking. The proposed monolithic 3D stacking designs can reduce not only the logic circuit area, but also interconnect length that makes wire routing resistance low and reduces the delay time. |
| 參考文獻 |
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