多模組之相位同步技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：25

、訪客IP：3.146.107.144

姓名

張家祥(Chia-Hsiang Chang ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

多模組之相位同步技術
(multiple module synchronization methodology)

相關論文

★ 匯流排上的時間延遲及交談失真的偵錯設計技巧	★ 適用於自動測試機台的時間產生器
★ 混波測試匯流排的量測學	★ 高速連結之時序與資料回復
★ 基於IEEE 1057之類比數位轉換器量測技術	★ 應用於高畫質電視之載波回復電路架構
★ 單晶片測試機之前端驅動電路設計	★ 系統晶片類比數位轉換器測試之數位信號處理程式庫
★ A 2.5V,0.35um,2.5Gbps 傳送接收器設計	★ 內建式類比數位/數位類比轉換器線性度之自我測試
★ 高準確度及低成本之電壓量測技術	★ 應用於ATSC VSB時脈回復之全數位延遲線迴路
★ 適用於晶片間通訊之高速傳輸介面	★ 內建式類比數位轉換器之自我校正方法
★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路	★ 高速傳輸連結網路的分析和模擬

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

我們在此提出一多模組相位同步技術。多模組的相位同步是個重要部分對於SOC系統的環境。所提出的同步技術目前是適合應用於整合自動測試機臺。此同步技術的優點是可很容易的增減所需同步模組的個數。同時能提供穩定同步且可調整的時序。而有了此同步且可調整的時序，我們可以用以取代原自動測試機臺的時序產生器。而此同步的機制可以簡化且縮減傳統所需的時序校正所需且冗長的時間。同步機制的模擬是先採用C語言描述加以模擬其機制動作，用以檢視其機制的運作。再來以Verilog硬體描述來模擬硬體實現的環境。模擬的環境設定成接近實際的運作環境。而同步機制所需的相位產生器是以TSMC 1p4m 0.35um 的製程技術設計製作。而其量測的結果可驗證其精細的相位解析度。

摘要(英)

In this thesis, we have proposed a novel methodology for multi-module synchronization. The multi-module synchronization is an important feature for SOC (system on a chip). The proposed synchronization methodology can also be fitted into the integration of ATE (automatic test equipment). The advantage of this methodology is easy to expand the number of modules without significant effort for the modification. It also provides highly stable synchronous timing and adjustable phase. With these, the synchronization mechanism can replace the original timing generator for the ATE. The synchronization mechanism also can simplify the con-ventional timing calibration process. The system simulation of the synchronization methodology is done in C language and Verilog. The simulation environment is set close to the condition of real environment. The component of multi-phase generator is designed with TSMC 1p4m 0.35um technology. The measurement results verify the generation of fine timing.

關鍵字(中)

★ 多模組相位同步技術
★ 時序產生器
★ 自動測試機臺

關鍵字(英)

★ ATE
★ synchronization methodology
★ timing generator

論文目次

Contents
CHAPTER 1INTRODUCTION1
1.1Motivation1
1.2Application in the integration of ATE4
1.3Timing generator5
1.4A dynamic clock synchronization technique7
1.5Point-to-point scheme8
1.6The issues in multi-module synchronization10
1.7Summary11
CHAPTER 2ARCHITECTURE OVERVIEW12
2.1Overview12
2.2Multi-module synchronization mechanism14
2.3Synchronization control logic20
2.4PN address reset finite state machine21
2.5Lead/Lag detection22
2.6PN/data combine24
2.7Data extraction25
2.8Phase compensation decision26
CHAPTER 3THEORETICAL BACKGROUNDS28
3.1Introduction28
3.2Analysis of “lead/lag detection”29
3.3Performance of confidence counter31
CHAPTER 4SIMULATION RESULT AND MEASUREMENT35
4.1Introduction35
4.2The simulation of NRZ clock recovery36
4.3The implementation of NRZ clock recovery37
4.4The measurement of NRZ clock recovery38
4.5Multi-module synchronization simulation result41
CHAPTER 5CONCLUSION47
BIBLIOGRAPHY48

參考文獻

[1]Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung, “A floorplan-based plan-ning methodology for power and clock distribution in ASICs [CMOS technol-ogy],” Proc. Design Automation Conference, 1999, pp. 766 —771.
[2]Pangjun, J.; Sapatnekar, S.S. “Clock distribution using multiple voltages,” Proc. Int'l Symp. Of Low Power Electronics and Design, 1999, pp. 145 —150.
[3]Taylor, G.F.; Geannopoulos, G. “Microprocessor clock distribution,” IEEE 5th Technical Meeting on Electrical Performance of Electronic Packaging, 1996, page 29.
[4]Ramanathan, P.; Dupont, A.J.; Shin, K.G. “Clock distribution in general VLSI circuits,” IEEE Trans. On Circuits and Systems I: Fundamental Theory and Applications, Vol 41 No. 5, 1994, pp. 395 —404.
[5]Restle, P.J.; Deutsch, A. “Designing the best clock distribution network,” Proc. Symp. On VLSI Circuits, 1998, pp. 2 -5.
[6]Aguiar, R.L.; Santos, D.M. “Wide-area clock distribution using controlled de-lay lines,” Proc. Int'l Conf. On Electronics, Circuits and Systems, 1998, pp. 63 -66 vol.2.
[7]Hyun Lee, Han Quang Nguyen, D.W. Potter, “Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback,” Proc. Int'l ASIC/SOC Conference, 2000, pp. 248 —252.
[8]Geannopoulos, G.; Dai, X. “An adaptive digital deskewing circuit for clock distribution networks,” Proc. Int'l Solid-State Circuits Conference, 1998, pp. 400 —401.
[9]Brueske, D.E.; Embabi, S.H.K. “A dynamic clock synchronization technique for large systems,” IEEE Trans. On Components, Packaging, and Manufactur-ing Technology, Part B: Advanced Packaging, Vol 17 No. 3, 1994, pp. 350 -361.
[10]Sutoh, H.; Yamakoshi, K.; Ino, M. “Circuit technique for skew-free clock dis-tribution,” Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995 , 1995 , Page(s): 163 -166
[11]Hong-Yean Hsieh; Wentai Liu; Clements, M.; Franzon, P. “Self-calibrating clock distribution with scheduled skews,” Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on, Volume: 2 , 1998,Page(s): 470 -473 vol.2.
[12]Hyun Lee; Han Quang Nguyen; Potter, D.W.,“Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback”
ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000 Page(s): 248 -252
[13]Kim, S.; Sridhar, R “Hierarchical synchronization scheme using self-timed mesochronous interconnections,” Proc. ISCAS 1997, pp. 1824 -1827 vol.3.
[14]Muttersbach, J.; Villiger, T.; Kaeslin, H.; Felber, N.; Fichtner, W “Glob-ally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems,” Proc. ASIC/SOC Conference, 1999, pp. 317 —321.
[15]Fenghao Mu; Svensson, C. “High speed interface for system-on-chip design by self-tested self-synchronization,” Proc. ISCAS 1999, pp. 516 -519 vol.2.
[16]S. Sidiropoulos, M.A. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. of Solid-State Circuits, Vol 32 No. 11, 1997, pp. 1683 -1692.
[17]Minami, K.; Mizuno, M.; Yamaguchi, H.; Nakano, T.; Matsushima, Y.; Sumi, Y.; Sato, T.; Yamashida, H.; Yamashina, M. “A 1 GHz portable digital de-lay-locked loop with infinite phase capture ranges,” Proc. Int'l Solid-State Cir-cuits Conf., 2000, pp. 350 -351.
[18]Garlepp, B.W.; et. al., “A portable digital DLL for high-speed CMOS interface circuits,” IEEE J. of Solid-State Circuits, Vol 34 No 5, 1999, pp. 632 —644.

指導教授

蘇朝琴(Chauchin Su)

審核日期

2001-7-3

推文