超大型積體電路連結系統測試與分析

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曾文亮(Wenliang Tseng) 查詢紙本館藏

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電機工程學系

論文名稱

超大型積體電路連結系統測試與分析
(Test and Analysis of VLSI Interconnect systems)

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摘要(中)

本論文是論述連接線模型(interconnect models)應用在超大型積體電路系統的廣泛工作，其適用於探討連接線模型對於高速數位訊號的影響。對於基本模型，我們使用線邏輯(wired-logic)針對單晶片(SoC)系統提出一個有效率的連接線自我測試方法來解決驅動電路互斥的問題。並且測試信號可以重複使用，錯誤涵蓋率也可以提高，測試時間也同時被縮短。電腦的模擬驗證了數學分析與推導的正確性，也再次肯定此一方法的可行性。其次是quasi-TEM 模型，對於一般用途的被動性(passive)傳輸線巨集模型(macromodel)在高速電路模擬環境上的發展，我們提出兩個主題。第一個主題是為了解決分佈性傳輸線(distributed trans-mission lime)其階梯網路(ladder network)在模型簡化(model order reduction)前的準確度問題。基於這個問題，我們提出一個新的準則，能使階梯網路的分段數量最小化，並確認其準確性。為了應付這個問題，對於有限與無限分段數的階梯網路，其互導矩陣(admittance matrix) 需要以極點-殘值對 (pole-residue pairs)的方式呈現。然而，在運算的過程中，面臨高電腦運算量的挑戰。因此，我們提出精簡式子(compact closed forms)來縮短整個估算執行過程。並經由合理的例子來描述這個準則的可行性。另一個主題是對於混合型傳輸線與RLC元件網路系統其模型簡化問題。根據Krylov-subspace演算法，我們提出一個新的技術以求得簡化的巨集模型。經由使用DEPACT技術，將這個複雜的網路系統轉換成線性時間延遲系統(linear time-delay system)。其關鍵性是使用基底轉換式(unified formulation)來保持其簡化模型的被動性(passivity)。我們也利用數學的證明和模擬結果證實所提技術的合法性。再者這個技術可延伸到控制系統中解模型簡化問題。由此，我們提出兩個定理來處理H-infinite範數有界(H-infinite norm bound)和被動性問題。根據定理，可藉由簡單線性矩陣不等式(linear matrix inequalities)的合適解(feasible solutions) 來得到簡化系統。因此，所提出的技術可提供一個有效率、準確和被動性的簡化系統應用在控制系統。

摘要(英)

This thesis is a comprehensive works of interconnect models in VLSI system. The relative works are suitable to explore the influence of interconnect models on high-speed digital signal. For basic models, the wired-logic is used to propose an efficient interconnect BIST methodology to deal with the tri-state driver contention problem. It also improves the fault coverage and makes pattern reuse possible for SoC system. Simulation results verify the mathematical analysis and reassure the feasibility the methodology. For quasi-TEM models, two tasks focus on the development of the gen-eral-purpose passive transmission line macromodel for a circuit simulation environ-ment. The first task is in order to solve the accuracy problem of model order reduction for ladder networks of distributed transmission lines. Base on that, this work proposes a new criterion to be able to minimize the number of ladder sections to ensure the ac-curacy. The pole-residue pairs of admittance matrix for the finite and infinite sections of ladder networks are required to address the criterion. However, the challenge is numerical computation of CPU cost. Therefore, this work proposes compact closed forms to overcome the difficulty. The valid examples delineate the feasibility of the proposed criterion. The other task is model order reduction problem for mixed dis-tributed transmission line/RLC component network system. A novel technique based on Krylov-subspace algorithm is proposed to obtain reduced macromodel. The com-plex network can transform into a linear time-delay system using DEPACT technique. A key feature of the proposed technique is using a unified formulation to preserve passivity. The mathematical derivation proof and simulation results approve the vali-dation of the proposed technique. Moreover, this technique is also extended to solve the H-infinite model order reduction problem in control system. Two theorems are proposed to deal with H-infinite norm bound and passivity problems. Based on the theorems, the re-duced system is obtained from the feasible solutions of simple linear matrix inequali-ties. Therefore, the proposed technique provides an efficient, accurate and passive re-duced system to application in control system.

關鍵字(中)

★ 自我建立測試
★ 傳輸線
★ 階梯網路
★ 模型簡化
★ 線性時間延遲系統

關鍵字(英)

★ Transmission Lines
★ Built-In Self Test
★ Ladder Networks
★ Model Order Reduction
★ Linear Time-delay System

論文目次

Contents iv
List of Figures vii
List of Tables ix
List of Acronyms x
List of Symbols xii
Chapter 1 Introduction 1
1.1. Motivation and Related Works 1
1.2. Contributions 6
1.3. Outline of Thesis 9
Chapter 2 Review of Interconnect Modeling and Simulation 10
2.1. Introduction 10
2.2. Interconnect Models 11
2.2.1. Wired-logic Models 12
2.2.2. Quasi-TEM Models 12
2.2.3. Full Wave Model 14
2.3. Frequency-domain Solutions 15
2.3.1. Decoupling of MTL Solution 16
2.3.2. Matrix Exponential of MTL Solutions 19
2.4. Formulation of Network Equations 20
2.4.1. Linear Networks 21
2.4.2. Distributed Networks 23
2.4.3. Embedded State-space Systems 24
2.5. MTL Macromodels 25
2.5.1. Ladder Networks 25
2.5.2. Method of Characteristics 27
2.5.3. Matrix Rational Approximation 29
2.5.4. DEPACT Technique 30
2.6. Model Order Reduction for RLC Circuits 33
2.6.1. Concepts of Moment Matching Techniques 33
2.6.2. Explicit Moment Matching Techniques 36
2.6.3. Implicit Moment Matching Techniques 39
2.7. Passivity Preservation 42
2.8. Summary 45
Chapter 3 Interconnect BIST Methodology 46
3.1. Introduction 46
3.2. BIST Methodology and Driver Cell Modification 48
3.2.1 Driver Cell Modification 49
3.2.2. BIST Architecture and Test Algorithms 52
3.3. Fault Coverage Analysis 55
3.4. Test Results 57
3.5. Summary 59
Chapter 4 Closed Form Analysis for Ladder Networks of Lossy Transmission Lines 65
4.1. Introduction 65
4.2. Formulation of Ladder Networks 67
4.3. The Closed Forms of Ladder Networks 70
4.4. Criterion of Number of Ladder Sections Required 79
4.5. Computational Results 85
4.6. Summary 90
Chapter 5 Passive Model Order Reduction of Interconnect Linear Time-delay System 93
5.1. Introduction 93
5.2. Formulation of Time-delay System 95
5.3. Reduction Algorithm Based on Congruent Transformation 99
5.4. Preservation of Moments 102
5.5. Passive Reduction of RLC Interconnects with Time-delay Systems 107
5.6. Passivity Preservation 110
5.7. Numerical Results 113
5.8. Summary 115
Chapter 6 Passive Model Order Reduction of General Linear Time-delay System 123
6.1. Introduction 123
6.2. Reduction Algorithm of Singular Linear Time-delay System 125
6.3. H-finite Model Reduction of Time-delay System 127
6.4. Strictly Passive Preservation 131
6.5. Numerical Results 133
6.6. Summary 135
Chapter 7 Conclusions and Future Works 137
7.1. Conclusions 137
7.2. Future Works 139
Bibliography 140
Appendix 149
List of Publications 154

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指導教授

蘇朝琴、劉建男
(Chauchin Su、Chien-Nan Jimmy Liu)

審核日期

2006-10-12

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