超大型積體電路連結系統測試與分析

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：32

、訪客IP：13.58.38.184

姓名

曾文亮(Wenliang Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

超大型積體電路連結系統測試與分析
(Test and Analysis of VLSI Interconnect systems)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 匯流排上的時間延遲及交談失真的偵錯設計技巧
★ 適用於自動測試機台的時間產生器	★ 混波測試匯流排的量測學
★ 高速連結之時序與資料回復	★ 基於IEEE 1057之類比數位轉換器量測技術
★ 應用於高畫質電視之載波回復電路架構	★ 單晶片測試機之前端驅動電路設計
★ 系統晶片類比數位轉換器測試之數位信號處理程式庫	★ A 2.5V,0.35um,2.5Gbps 傳送接收器設計
★ 內建式類比數位/數位類比轉換器線性度之自我測試	★ 高準確度及低成本之電壓量測技術
★ 應用於ATSC VSB時脈回復之全數位延遲線迴路	★ 適用於晶片間通訊之高速傳輸介面
★ 內建式類比數位轉換器之自我校正方法	★ 高速序列傳輸之量測技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文是論述連接線模型(interconnect models)應用在超大型積體電路系統的廣泛工作，其適用於探討連接線模型對於高速數位訊號的影響。對於基本模型，我們使用線邏輯(wired-logic)針對單晶片(SoC)系統提出一個有效率的連接線自我測試方法來解決驅動電路互斥的問題。並且測試信號可以重複使用，錯誤涵蓋率也可以提高，測試時間也同時被縮短。電腦的模擬驗證了數學分析與推導的正確性，也再次肯定此一方法的可行性。其次是quasi-TEM 模型，對於一般用途的被動性(passive)傳輸線巨集模型(macromodel)在高速電路模擬環境上的發展，我們提出兩個主題。第一個主題是為了解決分佈性傳輸線(distributed trans-mission lime)其階梯網路(ladder network)在模型簡化(model order reduction)前的準確度問題。基於這個問題，我們提出一個新的準則，能使階梯網路的分段數量最小化，並確認其準確性。為了應付這個問題，對於有限與無限分段數的階梯網路，其互導矩陣(admittance matrix) 需要以極點-殘值對 (pole-residue pairs)的方式呈現。然而，在運算的過程中，面臨高電腦運算量的挑戰。因此，我們提出精簡式子(compact closed forms)來縮短整個估算執行過程。並經由合理的例子來描述這個準則的可行性。另一個主題是對於混合型傳輸線與RLC元件網路系統其模型簡化問題。根據Krylov-subspace演算法，我們提出一個新的技術以求得簡化的巨集模型。經由使用DEPACT技術，將這個複雜的網路系統轉換成線性時間延遲系統(linear time-delay system)。其關鍵性是使用基底轉換式(unified formulation)來保持其簡化模型的被動性(passivity)。我們也利用數學的證明和模擬結果證實所提技術的合法性。再者這個技術可延伸到控制系統中解模型簡化問題。由此，我們提出兩個定理來處理H-infinite範數有界(H-infinite norm bound)和被動性問題。根據定理，可藉由簡單線性矩陣不等式(linear matrix inequalities)的合適解(feasible solutions) 來得到簡化系統。因此，所提出的技術可提供一個有效率、準確和被動性的簡化系統應用在控制系統。

摘要(英)

This thesis is a comprehensive works of interconnect models in VLSI system. The relative works are suitable to explore the influence of interconnect models on high-speed digital signal. For basic models, the wired-logic is used to propose an efficient interconnect BIST methodology to deal with the tri-state driver contention problem. It also improves the fault coverage and makes pattern reuse possible for SoC system. Simulation results verify the mathematical analysis and reassure the feasibility the methodology. For quasi-TEM models, two tasks focus on the development of the gen-eral-purpose passive transmission line macromodel for a circuit simulation environ-ment. The first task is in order to solve the accuracy problem of model order reduction for ladder networks of distributed transmission lines. Base on that, this work proposes a new criterion to be able to minimize the number of ladder sections to ensure the ac-curacy. The pole-residue pairs of admittance matrix for the finite and infinite sections of ladder networks are required to address the criterion. However, the challenge is numerical computation of CPU cost. Therefore, this work proposes compact closed forms to overcome the difficulty. The valid examples delineate the feasibility of the proposed criterion. The other task is model order reduction problem for mixed dis-tributed transmission line/RLC component network system. A novel technique based on Krylov-subspace algorithm is proposed to obtain reduced macromodel. The com-plex network can transform into a linear time-delay system using DEPACT technique. A key feature of the proposed technique is using a unified formulation to preserve passivity. The mathematical derivation proof and simulation results approve the vali-dation of the proposed technique. Moreover, this technique is also extended to solve the H-infinite model order reduction problem in control system. Two theorems are proposed to deal with H-infinite norm bound and passivity problems. Based on the theorems, the re-duced system is obtained from the feasible solutions of simple linear matrix inequali-ties. Therefore, the proposed technique provides an efficient, accurate and passive re-duced system to application in control system.

關鍵字(中)

★ 自我建立測試
★ 傳輸線
★ 階梯網路
★ 模型簡化
★ 線性時間延遲系統

關鍵字(英)

★ Transmission Lines
★ Built-In Self Test
★ Ladder Networks
★ Model Order Reduction
★ Linear Time-delay System

論文目次

Contents iv
List of Figures vii
List of Tables ix
List of Acronyms x
List of Symbols xii
Chapter 1 Introduction 1
1.1. Motivation and Related Works 1
1.2. Contributions 6
1.3. Outline of Thesis 9
Chapter 2 Review of Interconnect Modeling and Simulation 10
2.1. Introduction 10
2.2. Interconnect Models 11
2.2.1. Wired-logic Models 12
2.2.2. Quasi-TEM Models 12
2.2.3. Full Wave Model 14
2.3. Frequency-domain Solutions 15
2.3.1. Decoupling of MTL Solution 16
2.3.2. Matrix Exponential of MTL Solutions 19
2.4. Formulation of Network Equations 20
2.4.1. Linear Networks 21
2.4.2. Distributed Networks 23
2.4.3. Embedded State-space Systems 24
2.5. MTL Macromodels 25
2.5.1. Ladder Networks 25
2.5.2. Method of Characteristics 27
2.5.3. Matrix Rational Approximation 29
2.5.4. DEPACT Technique 30
2.6. Model Order Reduction for RLC Circuits 33
2.6.1. Concepts of Moment Matching Techniques 33
2.6.2. Explicit Moment Matching Techniques 36
2.6.3. Implicit Moment Matching Techniques 39
2.7. Passivity Preservation 42
2.8. Summary 45
Chapter 3 Interconnect BIST Methodology 46
3.1. Introduction 46
3.2. BIST Methodology and Driver Cell Modification 48
3.2.1 Driver Cell Modification 49
3.2.2. BIST Architecture and Test Algorithms 52
3.3. Fault Coverage Analysis 55
3.4. Test Results 57
3.5. Summary 59
Chapter 4 Closed Form Analysis for Ladder Networks of Lossy Transmission Lines 65
4.1. Introduction 65
4.2. Formulation of Ladder Networks 67
4.3. The Closed Forms of Ladder Networks 70
4.4. Criterion of Number of Ladder Sections Required 79
4.5. Computational Results 85
4.6. Summary 90
Chapter 5 Passive Model Order Reduction of Interconnect Linear Time-delay System 93
5.1. Introduction 93
5.2. Formulation of Time-delay System 95
5.3. Reduction Algorithm Based on Congruent Transformation 99
5.4. Preservation of Moments 102
5.5. Passive Reduction of RLC Interconnects with Time-delay Systems 107
5.6. Passivity Preservation 110
5.7. Numerical Results 113
5.8. Summary 115
Chapter 6 Passive Model Order Reduction of General Linear Time-delay System 123
6.1. Introduction 123
6.2. Reduction Algorithm of Singular Linear Time-delay System 125
6.3. H-finite Model Reduction of Time-delay System 127
6.4. Strictly Passive Preservation 131
6.5. Numerical Results 133
6.6. Summary 135
Chapter 7 Conclusions and Future Works 137
7.1. Conclusions 137
7.2. Future Works 139
Bibliography 140
Appendix 149
List of Publications 154

參考文獻

[1] H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, MA: Ad-dison-Wesley, 1990.
[2] C. Paul, Analysis of Multiconductor Transmission Lines. New York: Wiley, 1994.
[3] H. W. Jhonson and M. Grahaml, High-Speed Digital Design. Englewood Cliffs, NJ: Prentice-Hall, 1993.
[4] R. K. Poon, Computer Circuits Electrical Design. Englewood Cliffs, NJ: Pren-tice-Hall, 1995.
[5] A. Deustsch, "Electrical characteristics of interconnections for high-performance systems," Proc. IEEE, vol. 86, no. 2, pp. 315-355, Feb. 1998.
[6] R. Achar and M. Nakhla, "Simulation of high-speed interconnects," Proc. IEEE, vol. 89, pp. 693-728, May 2001.
[7] M. Nakhla and R. Achar, Multimedia Book Series on Signal Integrity. Ottawa, ON, Canada: OMNIZ Global Knowledge Corporation, 2002.
[8] R. Saleh, S. Jou, A. R. Newton, Mixed-mode simulation and analog multilevel simulation, Boston: Kluwer Academic, 1994.
[9] IEEE Std 1364 -2005, IEEE Standard for Verilog Hardware Description Lan-guage, IEEE Standard Board 2005.
[10] C. Chang and C. Su, "An Universal BIST Methodology for Interconnects," in Proc. Int'l Symp. on Circuits and Systems, 1992, pp.1615-1618.
[11] M. Lubaszewski and B. Courtois, "On the Design of Self-Checking Boundary Scanable Boards," in Proc. Int'l Test Conference, 1992, pp.372-381.
[12] C. Su, K. Hwang, and S. Jou, "An IDDQ Based Built-in Concurrent Test Technique for Intercon-nects in a Boundary Scan Environment," in Proc. Int'l Test Conference, 1994, pp.670-676.
[13] C. Su and S. J. Jou, "Decentralized BIST Methodology for System Level Inter-connects," Journal of Electronic Testing, 1999, pp. 255-265.
[14] D. Landis, C. Hudson, and P. McHugh, "Applications of the IEEE P1149.5 Module Test and Maintenance Bus," in Proc. Int'l Test Conference, 1992, pp.984-992.
[15] J. R. Griffith and M. Nakhla, "Time-domain analysis of lossy coupled trans-mission lines," IEEE Trans. Microwave Theory and Tech., vol. 38, pp. 1480-1487, Oct. 1990.
[16] J. B. Faria, Multiconductor Transmission Line Structures. New York: Wiley, 1993.
[17] E. Chiprout and M. Nakhla, "Analysis of interconnect networks using complex frequency hopping," IEEE Trans. Computer-Aided Design, vol. 14, pp. 186-199, Feb. 1995.
[18] A. E. Ruehli, Circuit Analysis, Simulation and Design. New York: Noth-Holland, 1988.
[19] J. K. White and A. S. Vincentelli, Relaxation Techniques for the Simulation of VLSI Circuits. Boston, MA: Kluwer, 1990.
[20] T. Dhaene and D. D. Zutter, "Selection of lumped element models for coupled lossy transmission lines," IEEE Trans. Computer-Aided Design, vol. 11, no. 7, pp. 805-815, July 1992.
[21] F. Y. Chang, "Transient analysis of lossless coupled transmission lines in a nonhomogeneous medium," IEEE Trans. Microwave Theory Tech., vol. MTT-18, pp. 616-626, Sept. 1970.
[22] F. C. M. Lau, "Waveform relaxation analysis of nonuniform lossy transmission lines characterized with frequency-dependent parameters," IEEE Trans. Cir-cuits Syst., vol. 38, pp. 1484-1500, Dec. 1991.
[23] S. Lin and E. S. Kuh, "Transient simulation of lossy interconnects based on the recursive convolution formulation," IEEE Trans. Circuits Systems I, vol. 39, pp. 879-892, NOV. 1992.
[24] D. B. Kuznetsov and J. E. Schutt-Ain, "Optimal transient simulation of trans-mission lines," IEEE Trans. Circuits Systems I, vol. 43, pp. 110-121, Feb. 1996.
[25] F. Y. Chang, "The generalized method of characteristics for waveform relaxa-tion analysis of lossy coupled transmission lines," IEEE Trans. Microwave Theory Tech., vol. 37, pp. 2028-2038, Dec. 1989.
[26] Q. Xu, Z. F. Li, P. Mazumder and J. F. Mao, "Time-domain modeling of high-speed interconnects by modified method of characteristics," IEEE Trans. Mi-crowave Theory and Tech., vol. 48, issue: 2, pp. 323- 327, Feb. 2000.
[27] A. Dounavis, X. Li, M. Nakhla, and R. Achar, "Passive closed-form transmis-sion-line model for general purpose circuit simulators," IEEE Trans. Micro-wave Theory Tech., vol. 47, no. 12, pp. 2450-2459, Dec. 1999.
[28] A. Dounavis, R. Achar, and M. Nakhla, "A general class of passive macro-models for lossy multiconductor transmission lines," IEEE Trans. Microwave Theory Tech., vol. 49, no. 10, pp. 1686-1696, Oct. 2001.
[29] A. Dounavis, R. Achar, and M. Nakhla, "Efficient passive circuit models for distributed networks with frequency-dependent parameters," IEEE Trans. Ad-vanced Packaging, vol. 23, pp. 382-392, Aug. 2000.
[30] N. Nakhla, A. Dounavis, R. Achar and M. Nakhla, "DEPACT: Delay Extrac-tion-Based Passive Compact Transmission-Line Macromodeling Algorithm", IEEE Trans. Advanced Packaging, vol. 28, pp. 13-23, Feb. 2005.
[31] N. Nakhla, A. Dounavis, M. Nakhla, R. Achar, "Delay-extraction-based sensi-tivity analysis of multiconductor transmission lines with nonlinear termina-tions," IEEE Trans. Microwave Theory and Tech., vol. 53, pp. 3520-3530, Nov. 2005.
[32] G. Shinh, N. Nakhla, R. Achar, M. Nakhla, A. Dounavis, I. Erdin, "Fast tran-sient analysis of incident field coupling to multiconductor transmission lines," IEEE Trans. Electromagnetic Compatibility, vol. 48, pp. 57-73, Feb. 2006.
[33] L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352–366, Apr. 1990.
[34] T. Tang and M. Nakhla, "Analysis of high-speed VLSI interconnect using as-ymptotic waveform evaluation technique," IEEE Trans. Computer-Aided De-sign, vol. 11, pp. 341-352, Mar. 1992.
[35] M. Celik and A. C. Cangellaris, "Efficient transient simulation of lossy pack-aging interconnects using moment-matching techniques," IEEE Trans. Comp. Packag. Manu. Tech., vol. B, vol. 19, pp. 64-73, Feb. 1996.
[36] P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Padé ap-proximation via the Lanczos process," IEEE Trans. Computer-Aided Design, vol. 14, pp. 639-649, May 1995.
[37] W. T. Beyene and J. E. Schutt-Aine, "Krylov subspace based modelorder re-duction techniques for circuit simulations," IEEE Trans. Midwest Circuits and Systems Symp., vol. 1, Aug. 1996, pp. 331-334.
[38] M. Silveria, M. Kamon, I. Elfadel, and J. White, "A coordinate transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of arbitrary RLC circuits," in Proc. IEEE ICCAD, pp. 288-294, Nov. 1996.
[39] M. Celik and A. C. Cangellaris, "Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques," IEEE Trans. Com-puter-Aided Design, vol. 16, pp. 485-496, May 1997.
[40] A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive reduced order intercon-nect macromodeling algorithm," IEEE Trans. Computer-Aided De-sign, vol. 17, no. 8, pp. 645-654, Aug. 1998.
[41] K. J. Kerns and A. T. Yang, "Preservation of passivity during RLC network reduction via split congruence transformations," IEEE Trans. Computer-Aided Design, vol. 17, pp. 582-591, July 1998.
[42] P. Gunupudi, M. Nakhla and R. Achar, "Simulation of high-speed distributed interconnects using Krylov-space techniques," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, issue 7, pp. 799-808, July 2000.
[43] L. Knockaert and D. D. Zutter, "Laguerre-SVD reduced-order modeling," IEEE Trans. Microwave Theory Tech., vol. 48, pp. 1469-1475, Sept. 2000.
[44] L. Knockaert and D. D. Zutter, "Stable laguerre-SVD reduced-order model-ing," IEEE Trans. Circuits and Systems I, vol. 50, pp. 576-579, Apr. 2003.
[45] J. R. Phillips, L. Daniel, and L. M. Silveira, "Guaranteed passive balancing transformations for model order reduction," IEEE Trans. Computer-Aided De-sign, vol. 22, pp. 1027-1041, Aug. 2003.
[46] S. Xu, J. Lam, S. Huang and C. Yang, "H-infinite model reduction for linear time-delay systems: continuous-time case," International Journal of control, vol. 74, no. 11, pp. 1062-1074, 2001.
[47] K. M. Grigoriadis, "Optimal H-infinite model reduction via linear matrix ine-qualities: continuous- and discrete-time cases," Systems & Control Letters, vol. 26, pp. 321-333, 1995.
[48] D. Kavranoglu and M. Bettayeb, "Characterization of the solution to the opti-mal H-infinite model reduction problem," Systems and Control Letters, vol. 20, pp. 99-107, 1993.
[49] L. Zhang, B. Huang and J. Lam, "H-infinite model reduction of Markovian jump linear systems," Systems & Control Letters, vol. 50, pp. 103-118, 2003.
[50] J. C. Willems, "Dissipative Dynamical Systems, Part I: General Theory," Arch. Rat. Mech. An., vol. 45, pp. 321-351, 1972.
[51] C. A. Desoer and M. Vidyasagar, Feedback Systems: Input-Output Properties. New York: Academic, 1975.
[52] R. A. Rohrer and H. Nosrati, “Passivity considerations in stability studies of numerical integration algorithms,” IEEE Trans. Circuits System, vol. CAS-28, pp. 857–866, Sept. 1981.
[53] H. J. Marquez and C. J. Damaren, "Comments on Strictly positive real transfer functions revisited," IEEE Trans. Automat. Contr., vol. 40, no. 3, pp. 478-479, March 1995.
[54] A. J. Schaft, L2-Gain and Passivity Techniques in Nonlinear Control, Springer, Communications and Control Engineering Series, 2000.
[55] S. I. Niculescu and R. Lozano, "On the Passivity of Linear Delay Systems," IEEE Trans. Automat. Contr., vol. 46, pp. 460-464, Mar 2001.
[56] R. F. Harrington, Time-harmonic electromagnetic fields, Boston: McGraw-Hill, 1993.
[57] D. G. Swanson, J. W. J. R. Hoefer, Microwave Circuit Modeling Using Elec-tromagnetic Field Simulation, Boston: Artech House, 2003.
[58] T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Circuits, vol. SSC-18, pp. 418-426, Aug. 1983.
[59] J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
[60] Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore delay for RLC trees," IEEE Trans. Computer-Aided Design, vol. 19, pp. 83-97, Jan. 2000.
[61] O. Palusinski and A. Lee, "Analysis of transients in nonuniform and uniform multiconductor transmission lines," IEEE Trans. Microwave Theory Tech., pp. 127-138, Jan. 1989.
[62] S. L. Manney, M. Nakhla, Q. J. Zhang, "Analysis of nonuniform, frequency-dependent high-speed interconnects using numerical inversion of Laplace transform," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 13, pp. 1513-1525, Dec. 1994.
[63] N. Boulejfen, A. Kouki, and F. Ghannouchi, "Frequency and time domain analysis nonuniform lossy coupled transmission lines with linear and nonlinear terminations," IEEE Trans. Microwave Theory Tech., pp. 367–379, Mar. 2000.
[64] A. Ruehli, "Equivalent circuit models for three-dimensional multiconductor systems," IEEE Trans. Microwave Theory Tech., vol. MTT-22, pp. 2 16-22 1, Mar. 1974.
[65] H. Heeb and A. E. Ruehli, "Three-dimensional interconnect analysis using par-tial element equivalent circuits," IEEE Trans. Circuits and Systems I, vol. 39, pp. 974-982, Nov. 1992.
[66] J. Ekman, G. Antonini, A. Orlandi and A. E. Ruehli, "Impact of partial element accuracy on PEEC model stability," IEEE Trans. Electromagnetic Compatibil-ity, vol. 48, pp. 19-32, Feb. 2006.
[67] A. E. Ruehli, H. Heeb, "Circuit models for three-dimensional geometries in-cluding dielectrics," IEEE Trans. Microwave Theory and Tech., vol. 40, pp. 1507-1516, July 1992.
[68] J. Cullum, A. Ruehli, T. Zhang, "A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation," IEEE Trans. Circuits and Systems II, vol. 47, pp.261-273, Apr. 2000.
[69] N. A. Marques, M. Kamon, L. M. Silveira, J. K. White, "Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects," IEEE Trans. Advanced Packaging, vol. 27, pp. 569-580, Nov. 2004.
[70] D. Saraswat, R. Achar, M. Nakhla, "Passive reduction algorithm for RLC in-terconnect circuits with embedded state-space systems (PRESS)," IEEE Trans. Microwave Theory and Tech., vol. 52, Part 2, pp. 2215-2226, Sept. 2004.
[71] D. Saraswat, R. Achar, M. Nakhla, "A fast algorithm and practical considera-tions for passive macromodeling of measured/simulated data," IEEE Trans. Advanced Packaging, vol. 27, no. 1, pp. 57-70, Feb. 2004.
[72] E. S. Kuh and R. A. Rohrer, Theory of Linear Active Networks. San Francisco: Holden-Day, 1967.
[73] B. C. Kuo, Automatic Control Systems, Prentice-Hall, 1995.
[74] Virtual Interface Proposal, VSI Alliance Revision 2.0 April 2001.
[75] IEEE Std 1500-2005, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits, IEEE-SA Standards Board 2005.
[76] IEEE 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Ar-chitecture, IEEE Standard Board 1990.
[77] The International Technology Roadmap for Semiconductors 2005 (2005 ITRS Roadmap), Semiconductor Industry Association (SIA), Apr. 18-20, 2005, http://public.itrs.net.
[78] A. J. Hassan, J. Rajski, and V. K. Agrawal, "Testing and Diagnosis of Inter-connects Using Boundary Scan Architecture," in Proc. Int'l Test Conference, 1988, pp.126-137.
[79] W. T. Cheng, J. L, Lewandowski, and L. Wu, "Diagnosis for Wiring Intercon-nects," in Proc. Int'l Test Conference, 1990, pp.565-571.
[80] R. Gupta, S. Kim and L. T. Pileggi, "Domian characterization of transmission line models and analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 2, pp. 184-193, Feb. 1996.
[81] T. Kailath, A. H. Sayed and B. Hassibi, Linear estimation, Prentice Hall, 2000.
[82] M. S. Ghausi and J. J. Kelly, Introduction to Distributed Parameter Networks, Hunting-ton, NY: R. E. Krieger, 1977.
[83] S. G. Chrystal, Textbook of Algebra, New York, Chelsea, 1961.
[84] F. Tisseur and M. Karl, "The quadratic eigenvalue problem," SIAM Review, vol. 43, no. 2, pp. 235-286, 2001.
[85] J. Dedieu and F. Tisseur, "Perturbation theory for homogeneous polynomial eigenvalue problems," Linear Algebra Appl., vol. 358, pp. 71-94, 2003.
[86] Y. Tanji, A. Ushida and M. Nakhla, "Passive closed-form expression of RLCG transmission lines," in Proc. ISCAS’02, vol. 3, pp. 795-798, May 2002.
[87] Y. Tanji and H. Asai, "Closed-form expressions of distributed RLC intercon-nects for analysis of on-chip inductance effects," in Proc. DAC’04, pp. 810-813, June 2004.
[88] S. L. Campbell and C. D. J. Meyer, Generalized Inverses of Linear Transfor-mations. New York: Dover, 1991.
[89] F. Szidarovszky, O. A. Palusinski, "Clarification of a decoupling method for multiconductor transmission lines," IEEE Trans. Microwave Theory and Tech., vol. 47, issue 6, pp. 798-801, June 1999.
[90] K. Glover, "All optimal Hankel-Norm approximations of linear multivariable systems and their L-infinite error bounds," International Journal of Control, vol. 39, pp. 1115-1193, 1984.
[91] L. Zhang and J. Lam, "Optimal weighted L2 model reduction of delay sys-tems," International Journal of control, vol. 72, no. 1, pp. 39-48, 1999.

指導教授

蘇朝琴、劉建男
(Chauchin Su、Chien-Nan Jimmy Liu)

審核日期

2006-10-12

推文