LPDDR5 基板電路高速訊號完整性分析

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姓名

陳俊甫(Chun-Fu Chen) 查詢紙本館藏

畢業系所

通訊工程學系在職專班

論文名稱

LPDDR5 基板電路高速訊號完整性分析
(High-Speed Signal Integrity Analysis of LPDDR5 Substrate)

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摘要(中)

近年來電子產品講求輕、快、薄，加上AI的崛起，記憶體也需要更快的存取速度，而低功率記憶體進入到第五代的技術，工作頻率也更加的快速，在高頻下，訊號完整性的問題更加的重要。
本論文會針對三個部份來進行討訊號完整性討論，第一部分為封裝型型態對於訊號完整性的影響，第二部分為基板結構設計對於訊號完整性的影響，第三部分為Layout設計對於訊號完整性的影響，透過這三部分的研究來找出第五代低功率記憶體的基板設計方向。

摘要(英)

In recent years, e lectronic products emphasize lightness, fast, and
thinness. With the rise of artificial intelligence, memory also needs to be
accessed faster. Low power memory has entered the fifth generation of
technology and operates more frequently. At high frequencies , signal
integrity becomes more important.
This article discusses signal integrity in the following three aspects.
The first part examines the effect of package type on signal integrity. The
second part focuses on the impact of substrate structure desi gn on signal
integrity. Finally, the third part examines the impact of layout design on
signal integrity. Through these three studies, we aim to determine the
substrate design direction for the fifth generation of low power memory.

關鍵字(中)

★ LPDDR
★ 訊號完整性

關鍵字(英)

★ LPDDR
★ Signal Integrity

論文目次

第１章緒論------------------------------1
１.１研究動機----------------------------1
１.２文獻回顧----------------------------1
１.３研究方法----------------------------4
１.４論文架構----------------------------5
第２章訊號完整性基本原理------------------6
２.１傳輸線原理與特徵阻抗-----------------6
２.２微帶線與帶狀線之特徵阻抗-------------9
２.３ S參數------------------------------10
２.４眼圖-------------------------------11
２.５傳輸線損耗--------------------------13
第３章封裝型態訊號完整性分析---------------14
３.１打線與覆晶製程簡介-------------------14
３.２打線與覆晶製程於LPDDR5設計差異--------16
３.３模擬環境與參數設定-------------------17
３.４打線與覆晶製程S參數分析--------------19
３.５打線與覆晶製程眼圖分析---------------21
第４章基板結構設計模擬分析----------------24
４.１模擬環境與參數設定-------------------25
４.２膠片厚度改變對於訊號完整性影響--------26
4.2.1 膠片厚度改變的S參數分析------------27
4.2.2 膠片厚度改變的眼圖分析-------------28
４.３介電系數改變對於訊號完整性影響--------30
4.3.1 介電系數改變的S參數分析------------31
4.3.2 介電系數改變的眼圖分析-------------32
４.４損耗因子改變對於訊號完整性影響--------33
4.4.1 損耗因子改變的S參數分析------------34
4.4.2 損耗因子改變的眼圖分析-------------35
４.５基板結構設計總結---------------------37
第５章 Layout設計模擬分析 -----------------38
５.１ L2參考層挖空設計---------------------38
5.1.1 L2參考層挖空設計S參數-------------39
5.1.2 L2參考層挖空設計眼圖分析-----------39
５.２ Via and Anti-Pad gap設計------------40
5.2.1 Anti-Pad gap設計S參數分析----------41
5.2.2 Anti-Pad gap設計眼圖分析-----------42
5.2.3 僅在L2層進行Anti-Pad gap設計分析---44
５.３ Layout設計總結-----------------------46
結論--------------------------------------47
參考文獻----------------------------------49

參考文獻

[1] Eric Bogatin, “Signal and Power Integrity, 3rd ed. ” Prentice Hall,2018.
[2] B. D. Jarvis, “The effects of interconnections on high-speed logic circuits, ”IEEE Trans. Electron. Comput., vol. 12,no. 5, pp. 476-487, Oct.1963.
[3] C. S. Chang, “An overview of computer packaging architecture and electrical design, ”Proceedings of the 1990 IEEE Southern Tier Technical Conference, pp. 239-257, Binggamton, NY, USA, April 1990.
[4] M. H. Wu,W. J. Chen,J. W. Liang, X. B. Fang, “An improvement method of the increasing mutual capacitance for reducing far-end crosstalk in transmission line, ”IEEE Antennas and Propagation Society International Symposium, pp.1227-1230, July 2006.
[5] Farhang Yazdani, “Wirebond Vs. flip chip design of high speed 3D stacked memory packages,” 2nd Asia Symposium on Quality Electronic Design (ASQED), pp 332-336, August 2010.
[6] HoJeong Lim, JeongKyu Yang, HeeYeon Ku, “High-speed flip chip package Co-Design with Optimization of Anti-Pad gap size variations on metal plane layout, ” 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), May 2016
[7] 蔡政憲,“防護線對高速數位信號在板級的電磁干擾影響探討,”交通大學碩士論文,2009.
[8] Kyoungho Lee, Hyun-Bae Lee, Hae-Kang Jung, Jae-Yoon Sim “A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing Jitter of Parallel Microstrip Lines”, IEEE Transactions On Advanced Packaging, VOL. 31, NO. 4, November 2008.
[9] 趙嘉瀅,“使用接地防護線降低串音雜訊,” 臺灣大學碩士論文, 2006.
[10] Isao Nishimura, Shintarou Fujitomi, Yuutoku Yamashita, “Development of new dielectric material to reduce transmission loss,” 2020 IEEE 70th Electronic Components and Technology Conference (ECTC),pp 641-646, June 2020
[11] Takashi Tasaki, Atsushi Shiotani, Takashi Yamaguchi, “Low Dk/Df polyimide adhesives for low transmission loss substrates, ” 2017 International Conference on Electronics Packaging (ICEP), pp 424-429, April 2017.
[12] 車偉民,“不同玻璃纖維結構介質下差模信號線之訊號完整性,” 中原大學碩士論文,2020.
[13] JESD209-5B, https://www.jedec.org/, Jun 2021.
[14] 蕭嵩齡,“ 結合IBIS模型之電路板層級EMC分析,” 大葉大學碩士論文,2015.
[15] 王郁誠, “ 用頻域模擬法探討S參數及其應用,” 中央大學碩士論文,2007.
[16] 吳忠儒, “ 用時域模擬法探討S參數及其應用,” 中央大學碩士論文,2005.
[17] 郭維德,“ 印刷電路板級損耗傳輸線之眼圖分析與補償設計,” 台灣大學碩士論文,2005.
[18] W.-D. Guo, F.-N. Tsai, G.-H. Shiue, and R.-B. Wu, “Reflection enhanced compen- sation of lossy traces for best eye-Diagram improvement using high-impedance mismatch,” IEEE Trans. Adv. Packag., vol. 31, no. 3, pp. 619-626, Aug. 2008.
[19] H.A. Wheeler, “Transmission-Line Properties of Parallel Wide Strips by a Conformal-Mapping Approximation, ” IEEE Transactions on Microwave Theory and Techniques , Volume 12, Issue 3, p.280-289, May 1964.
[20] E. O. Hammerstad, “ Equations for Microstrip Circuit Design, ”1975 5th European Microwave Conference, p.268–272, September 1975.
[21] Design Guide for High-Speed Controlled Impedance Circuit Boards,https://www.ipc.org/, March 2004.
[22] S.B. Cohn, “Problems in Strip Transmission Lines, ” IRE Transactions on Microwave Theory and Techniques.,vol.3, Issue 2,pp.119-126, March 1955.
[23] O. L. Anderson; H. Christensen; P. Andreatch, “Technique for Connecting Electrical Leads to Semiconductors, ” Journal of Applied Physics 28, p.923,May 1957.
[24] A.P. Youmans, R.E. Rose, W.F. Greenman, “A multichip package utilizing in-Cu flip-chip bonding, ” Proceedings of the IEEE, Volume 57, Issue 9, pp.1599-1605, September 1969.
[25] 李岳勳,“DDR高速訊號傳輸之訊號完整性模擬分析,”逢甲大學碩士論文,2022.

指導教授

張大中

審核日期

2023-7-11

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