5.2GHz CMOS射頻接收器前端電路設計

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姓名

梁志維(chi-wei liang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

5.2GHz CMOS射頻接收器前端電路設計
(5.2GHz CMOS RF Receiver Frond-end Circuits Design)

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摘要(中)

本論文介紹一個使用台積電 0.18微米CMOS製程所實現的射頻前端電路，他是適用於 5-GHz ISM頻段。這個前端電路在輸入端使用了一個低雜訊放大器. 接下來的混波器電路包含了一個對稱式被動單雙轉換器以實現雙平衡架構的混波器。六階的多相位濾波器和高線性度的內部緩衝器能排拒鏡像信號超過60dB。整體接收器在1.8V的電壓下有30mW的功率，高準度的四相位同步震盪器提供了接收器所需的本地信號，這個震盪器使用1/9的輸出頻率來進行鎖定，這個震盪器也有效簡化整體頻率產生器設計的效果。

摘要(英)

The radio frequency (RF) front-end of the wireless communication systems such as cellular phones, cordless phone, and personal communication system (PCS) are almost implemented by GaAs or Bipolar technologies due to their good performance in high frequency. However, the rapid advancement and scaling of the size done in CMOS technology, which now offers higher unity current gain cut off frequency (fT) and maximum operatng frequency (fmx), has been comparaed with GaAs and Bipolar.
A RF frond-end circuit fabricated in TSMC 0.18um CMOS technology is presented in this thesis. It is suitable for 5-GHz ISM band. This frond-end circuit adopted a low-noise amplifier with single input. A symmetric passive balun is included in the mixer circuit to implement the double-balance mixer. The 6-stage polyphase filter and high linearity inter-stage buffer reject the image band more than 60dB. The overall receiver consumes 30mW with 1.8V supply voltage. The local signal is supplied by a high accuracy quadrature synchronous oscillator. This oscillator is locked by using 1/9 output frequency signal. This synchronous oscillator simplifies the frequency generator design.

關鍵字(中)

★ 射頻
★ 接收器
★ 電路

關鍵字(英)

★ CMOS
★ RF
★ receiver
★ circuit

論文目次

Abstract i
Content i
List of Figures v
List of Tables ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Receiver Overview 1
2.1 Introduction 1
2.2 Performance Parameters 2
2.2.1 Noise Figure 2
2.2.2 Gain Compression 3
2.3 3rd-Order Intermodulation 5
2.4 Receiver Architecture Overview 7
2.4.1 Superheterodyne Receiver 7
2.4.2 Direct-Conversion Receiver 8
2.4.3 Wide-band IF Receiver 9
2.4.4 Low-IF Receiver 10
2.5 Receiver Front-end Architecture in This Work 11
2.6 The IEEE 802.11a Specification 12
Chapter 3 Low Noise Amplifier 15
3.1 Introduction 15
3.2 Noise Model in CMOS Device 15
3.3 Several LNA topologies 17
3.4 LNA Design 18
3.4.1 Input Matching 19
3.4.2 Noise Figure Analysis 21
3.4.3 Noise Figure Optimization Techniques [10] 23
3.4.4 Gain 24
3.4.5 LNA Design Flow 26
3.5 Simulation Result 27
3.6 Layout Concern and Physical Layout 32
3.6.1 Dual-Gate MOSFET [17][18] 32
3.6.2 Shielded PAD 33
3.6.3 Physical Layout 34
Chapter 4 Mixer 35
4.1 Introduction 35
4.2 The Several Mixer types 35
4.2.1 Passive and Active Mixer 36
4.2.2 Single-Balanced and Double-Balanced Mixers 37
4.3 Low Supply Voltage Mixer Design 38
4.4 The Mixer in this Work 40
4.4.1 On-Chip Balun 41
4.4.2 Conversion Gain Analysis 42
4.4.3 Noise 43
4.4.4 Linearity 43
4.5 Simulation Result 44
4.6 Physical Layout 45
Chapter 5 Image-Rejection Block 47
5.1 Introduction 47
5.2 Polyphase Network 47
5.2.1 Behavior of Phasephae Filter 48
5.2.2 Image Rejection using Polyphase Filter 49
5.2.3 Practical Considerations 51
5.3 Polyphase Filter Design 53
5.4 Inter-Stage Buffer Design 54
5.5 Simulation Result 57
5.6 Overall Receiver Simulation Result 59
Chapter 6 Quadrature-phase Synchronous Oscillator 62
6.1 Introduction 62
6.2 Synchronous Oscillator 63
6.2.1 Synchronization Idea 63
6.2.2 The Synchronization Pulse Width Optimal 64
6.2.3 Overall Synchronous Oscillator 65
6.2.4 Output Buffer 66
6.2.5 I/Q Clock Generator 67
6.2.6 Pulse Implementation 68
6.3 Simulation Result 69
6.4 Summary 72
Chapter 7 Conclusion 74
Bibliography 75

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指導教授

劉建男(Chien-Nan Liu)

審核日期

2002-10-8

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