撞擊游離的等效電路模型與其在半導體元件模擬上之應用

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姓名

李思儒(Szu-Ju Li) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

撞擊游離的等效電路模型與其在半導體元件模擬上之應用
(An Equivalent Circuit of Impact-Ionization and its Applications on Semiconductor Devices)

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摘要(中)

本論文主要以分析撞擊游離(impact-ionization)的機制並建立一維及二維的撞擊游離等效電路模型。在二維模型的建立上，我們同時探討於二維x-y方向的電場與電流密度分布以及撞擊游離的機制在描述元件的接面上所發生的累增崩潰(avalanche breakdown)。因此，在建立起一維及二維撞擊游離等效電路模型後，我們使用一維及二維的二極體與雙載子接面電晶體來驗證其模型的正確性並比較其撞擊游離的機制效應。在撞擊游離等效電路模型的應用上，我們使用Thyristor功率元件來觀察撞擊游離的效應。同時於更深入的呈現元件的SCR特性曲線，我們利用了調變外加電壓移動負載線(load line)來尋找保持電流(holding current)。最後，在Thyristor功率元件的模擬方面，面臨到數值運算上的困難，因此我們採用regrid的方法來加強程式的收斂性。

摘要(英)

In this thesis, we analyse the impact-ionization mechanism and build up 1D and 2D impact-ionization circuit model. In 2D environment, we study the two- dimensional x-y directions distributions in electric field and current density. The impact-ionization mechanism causes the junction avalanche breakdown. Therefore, after building up the 1D and 2D impact-ionization model, we use 1D and 2D PN diode and BJT for verification. In device application, we use the power device thristor to observe impact-ionization effects. To present complete SCR characteristics, we use the load line concept with modulating applied bias to find the holding current. Last, in SCR simulation, we face the numerical computing challenge, and we use the regrid method to enhance the program convergence.

關鍵字(中)

★ 撞擊游離
★ 等效電路模型
★ 半導體元件模擬

關鍵字(英)

★ impact ionization
★ simulation
★ SCR

論文目次

1. Introduction
2. One-dimensional Impact-Ionization Modeling
2.1 1D Equivalent Circuit Model
2.2 The Impact-Ionization Current Model
2.2.1 Impact-Ionization Generation Mechanism
2.2.2 Impact-Ionization Circuit Model
2.2.3 1D Model with Impact-Ionization Circuit
2.3 Verification of the 1D Model with Impact-Ionization
2.3.1 The 1D PN Diode Simulation
2.3.2 The 1D BJT Simulation
2.3.3 Discussion
3. Two-dimensional Impact-Ionization Modeling
3.1 2D Equivalent Circuit Model
3.2 The Impact-Ionization Current Model
3.2.1 The Phenomenon of the Electric Field and Generation Rate in a Rectangular Grid
3.2.2 2D Model with Impact-Ionization Circuit
3.3 Verification of the 2D Model with Impact-Ionization
3.3.1 The 2D PN Diode Simulation
3.3.2 The 2D BJT Simulation
4. Application in Impact-Ionization Circuit Model with PNPN SCR
4.1 The PNPN SCR Operational Theory
4.2 The PNPN Simulation
4.2.1 The 1D PNPN SCR Simulation
4.2.2 The 2D PNPN SCR Simulation
4.2.3 The Gate Voltage Considerations
4.3 Improvement on SCR Device Simulation
4.3.1 Practical Holding Current Considerations
4.3.2 Investigation on Program Convergence
5. Conclusion

參考文獻

[1] B.K. Johnson and H.L. Hess, "Power semiconductors," IEEE Power Engineering Society Winter Meeting, 2001., vol. 2 , pp. 734-735, 2001.
[2] M. Shur, Introduction to Electronic Devices, Chapter 3, John Wiley & Sons Inc., 1996.
[3] E. S. Yang, Microelectronic Devices, Chapter 5, McGRAW-HILL, 1988.
[4] S. Selberherr, Analysis and Simulation of Semiconductor Devices, Chapter 4, Springer-Verlag Wien, 1984.
[5] C.-C. Chang, "Verification of 1D BJT Numerical Simulation and its Application to Mixed-level Device and Circuit Simulation," M. S. Thesis Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2001.
[6] R. F. Pierret, Semiconductor Device Fundamentals, Chapter 13, Addison Wesley, 1996.
[7] M. Hatle and J. Vobecky, " A New Approach to the Simulation of Small-Signal Current Gains of pnpn Structures," IEEE Transactions on Electron Devices, vol. 40, no. 10, pp. 1864-1866, Oct. 1993.
[8] Z. Lisik and M. Turowski, "Two-dimensional simulation of thyristor transient states from conduction to forward blocking," IEE Proceedings G, vol. 138, no. 5, pp. 575-581, Oct. 1991.
[9] A. Brambilla and E. Dallago, "A Circuit-Level Simulation Model of PNPN Devices," IEEE Transactions on Computer-Aided Design, vol. 9, no. 12, pp. 1254-1264, Dec. 1990.
[10] E. Masada, M. Tamura and T. Nakajima, “Simulation of switching processes in turn-off thyristors,” Power Electronics Specialists Conference, 1988. PESC ’’88 Record., 19th Annual IEEE, vol. 1, pp. 91-98, 1988.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2002-6-28

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