針對多通道三維隨機存取記憶體之測試和良率增進技術

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吳冠德(Kuan-Te Wu) 查詢紙本館藏

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電機工程學系

論文名稱

針對多通道三維隨機存取記憶體之測試和良率增進技術
(Testing and Yield-Enhancement Techniques for Multi-Channel 3D DRAMs)

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至系統瀏覽論文 (2028-8-18以後開放)

摘要(中)

使用穿矽孔三維整合技術提供了許多不同於二維整合技術的好處，像是低功耗、高效能、體積小、異質整合等等。三維整合技術已被廣泛使用在動態隨機存取記憶體中，使其達到更高的記憶體密度和更高的效能。三維動態隨機存取記憶體由多個通道所組成，以提供更寬的資料頻寬；然而，以穿矽孔為基底的三維動態隨機存取記憶體能否量產的兩大關鍵在於其測試及良率。
在本文的第一部分，提出了針對多通道維動態隨機存取記憶體其通道間可共享內建式自我測試架構，此內建式自我測試架構能處理多通道間不同讀取和寫入延遲的情況下，同時提供測試圖樣給多通道並且依其回傳的資料判斷其是否有錯，實驗模擬結果顯示，在一個雙通道1G位元的多通道動態隨機存取記憶體，所提出來的內建式自我測試架構與現存的共享內建式自我測試架構來做比較，最高能達到降低11%的測試時間且所付出的面積成本僅有0.003%。
在本文的第二部分，我們介紹針對多通道三維動態隨機存取記憶體以點對點匯流排為基底的輸入輸出介面，根據此輸入輸出介面，我們提出錯誤容忍架構，其能容忍在此介面的錯誤瑕疵，如此多通道三維動態隨機存取記憶體的良率便能被提升。提出的錯誤容忍架構是使用通道間重組機制來容忍在輸入輸出介面的穿矽孔和微凸塊其錯誤瑕疵，此外，也提出錯誤演算法來找出在穿矽孔和微凸塊的斷開瑕疵，進一步，我們也針對多通道三維動態隨機存取記憶體設計內建式自我修復電路，其能執行找出錯誤位址的測試演算法並產生重組的控制訊號。分析結果顯示，相較現存的通道間重組架構，我們所提出的錯誤容忍架構能提升良率達23%。我們所實現的內建式自我修復電路是使用TSMC 65nm LP的製程技術來合成，針對16個通道且每個通道的資料寬為128位元的多通道三維動態隨機存取記憶體，我們所提出的架構僅增加0.28%的硬體成本。

摘要(英)

Three-dimensional (3D) integration technology using through silicon via (TSV) offers many benefits over 2D integration technology, such as low power, high performance, small footprint, heterogeneous integration etc. 3D integration technology has been used to realize dynamic random access memories (DRAMs) that provides higher memory density and higher performance than modern 2D DRAMs. 3D DRAMs typically have multiple channels to provide more data bandwidth. However, testing and yield are two key challenges of the TSV-based3D DRAMs for the volume production.
In the first part of the thesis, a channel-shareable built-in self-test (BIST) scheme for multi-channel 3D DRAMs is proposed. The BIST scheme is capable of applying test pat-terns and evaluating test responses for multiple channels simultaneously, regardless of the read/write latency differences among the channels. As a result, the proposed BIST scheme can significantly reduce the test time. The simulation results show that the proposed BIST scheme can achieve about 11% test time reduction compared to the existing shared BIST scheme for a two-channel 1G-bit DRAM, by paying only about 0.003% area cost.
In the second part of the thesis, we introduce a point-to-point bus-based IO interface for multi-channel 3D DRAMs. Based on the IO interface, we propose a fault-tolerant scheme to tolerance the defects in IO interface such that the yield of multi-channel 3D DRAMs can be improved. The proposed fault-tolerance scheme uses intra-channel and inter-channel reconfiguration mechanisms to tolerance the defects in TSVs and micro bumps of the IO interface. Also, a fault-location algorithm is proposed to locate the positions of open defects. Furthermore, we design a built-in self-repair (BISR) circuit which can generate the proposed fault-location test algorithm and reconfiguration control signals for 3D DRAMs. Analysis results show that the proposed fault-tolerance scheme can achieve above 23% yield gain compared to the existing inter-channel reconfiguration scheme. The BISR designed with TSMC 65nm LP process technology incurs only about 0.28% hardware overhead for a 3D DRAM with 16 channels in which each channel has 128 bits.

關鍵字(中)

★ 測試
★ 良率增進
★ 多通道
★ 三維隨機存取記憶體

關鍵字(英)

★ Testing
★ Yield-Enhancement
★ Multi-Channel
★ 3D DRAM

論文目次

1 Introduction 1
1.1 3D DRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 TSV and Bonding Techniques . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Multi-Channel 3D DRAM . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Test and Yield-Enhancement Techniques for Multi-Channel 3D DRAMs . . . 4
1.2.1 Existing Test Techniques . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Yield-Enhancement Techniques for Multi-Channel 3D DRAMs . . . . 5
1.3 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 A BIST Scheme for Multi-Channel 3D DRAMs 7
2.1 Memory Controller for Multi-Channel 3D DRAMs . . . . . . . . . . . . . . . 8
2.2 Proposed Channel-Shareable BIST Architecture . . . . . . . . . . . . . . . . 10
2.3 Proposed Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 Analysis and Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 A BISR Scheme for Multi-Channel DRAMs with Intra-Channel Reconfig-
uration Mechanism 24
3.1 Existing Fault-Tolerance Design for Multi-Channel 3D DRAMs . . . . . . . 24
3.2 Proposed Fault-Tolerance Scheme with Intra-Channel Reconfiguration Mech-
anism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Fault-Tolerance Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.2 Intra-Channel Reconfiguration Mechanism . . . . . . . . . . . . . . . 27
3.2.3 Fault-Tolerant Multi-Channel 3D DRAM Architecture . . . . . . . . 29
3.2.4 Tolerable Faults and Test Algorithm . . . . . . . . . . . . . . . . . . 30
3.3 Proposed Built-In Self Repair . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.1 Proposed Multi-Channel 3D DRAM Implementation . . . . . . . . . 33
3.3.2 Test Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.3 Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 Yield Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.1 Yield Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Conclusion and Future Work 48
4.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

參考文獻

[1] S. Deutsch, B. Keller, V. Chickermane, S. Mukherjee, N. Sood, S. K. Goel, J.-J. Chen, A. Mehta, F. Lee, and E. J. Marinissen, “DfT architecture and ATPG for interconnect tests of JEDEC wide-I/O memory-on-logic die stacks,” in Proc. Int’l Test Conf. (ITC), Nov. 2012, pp. 1–10.
[2] T.-Y. Oh, K.-I. Park, Y.-S. Yang, Y.-S. Sohn, S.-H. Kim, and S.-J. Bae, “Stacked semiconductor memory device, memory system including the same, and method of repairing defects of through silicon vias,” U.S Patent No. 8654593 B2, Apr. 2011.
[3] Y. Xie, G. H. Loh, B. Black, and K. Bersnstein, “Design space exploration for 3D architectures,” ACM Journal on Emerging Technologies in Computing Systems, vol. 2, no. 2, pp. 65–103, Apr. 2006.
[4] J.-Q. Lu, “3-D hyperintegration and packaging technologies for micro-nano systems,” Proceedings of the IEEE, vol. 97, no. 1, pp. 18–30, Jan. 2009.
[5] M. Motoyoshi, “Through-silicon via (TSV),” Proceedings of the IEEE, vol. 97, no. 1, pp. 43–48, Jan. 2009.
[6] U. Kang and et al., “8Gb 3-D DDR3 DRAM using through-silicon-via technology,” IEEE Jour. of Solid-State Circuits, vol. 45, no. 1, pp. 111–119, Jan. 2010.
[7] T. Sekiguchi, K. Ono, A. Kotabe, and Y. Yanagawa, “1-Tbyte/s 1-Gbit DRAM architec- ture using 3-D interconnect for high-throughput computing,” IEEE Jour. of Solid-State Circuits, vol. 46, no. 4, pp. 828–837, Apr. 2011.
[8] J.-S. Kim and et al., “A 1.2V 12.8 GB/s 2Gb mobile wide-I/O DRAM with 4x128 I/Os using TSV based stacking,” IEEE Jour. of Solid-State Circuits, vol. 47, no. 1, pp. 107–116, Jan. 2012.
[9] C.Weis, I. Loi, L. Benini, and N.Wehn, “Exploration and optimization of 3-D integrated DRAM subsystems,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 597–610, April 2013.
[10] JEDEC, “JEDEC wide I/O single data rate,” http://www.jedec.org/, Dec. 2011.
[11] ——, “DDR4 SDRAM,” http://www.jedec.org/, Sep. 2012.
[12] ——, “JEDEC high bandwidth memory (HBM) DRAM,” http://www.jedec.org/, Oct. 2013.
[13] B.Wang and Q. Xu, “Test/repair area overhead reduction for small embedded SRAMs,” in IEEE Asian Test Symp. (ATS), Nov. 2006, pp. 37–44.
[14] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal, “A serial interfacing technique for built-in and external testing of embedded memories,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), San Diego, May 1989, pp. 22.2/1–22.2/5.
[15] W.-B. Jone, D.-C. Huang, S.-C. Wu, and K.-J. Lee, “An efficient BIST method for small buffers,” in Proc. IEEE VLSI Test Symp. (VTS), 1999, pp. 246–251.
[16] V. Arora, W.-B. Jone, D.-C. Huang, and S. R. Das, “A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays,” IEEE Trans. on Instru- mentation and Measurement, vol. 53, no. 4, pp. 915–932, Aug. 2004.
[17] L.Wu, C.Weaver, and T. Austin, “CryptoManiac: A fast flexible architecture for secure communication,” in Proc. 28th Ann. Int’l Symp. on Computer Architecture, 2001, pp. 110–119.
[18] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Au- tomatic generation of memory built-in self-test cores for system-on-chip,” in IEEE Asian Test Symp. (ATS), Nov. 2001, pp. 91–96.
[19] Y.-J. Huang and J.-F. Li, “A low-cost pipelined BIST scheme for homogeneous rams in multicore chips,” in IEEE Asian Test Symp. (ATS), Nov. 2008, pp. 357–362.
[20] M. Miyazaki, T. Yoneda, and H. Fujiwara, “A memory grouping method for sharing memory BIST logic,” in Proc. Asia and South Pacific Design Automation Conf. (ASP- DAC), Jan. 2006, pp. 671–676.
[21] L. Martirosyan, G. Harutyunyan, S. Shoukourian, and Y. Zorian, “A power based memory BIST grouping methodology,” in IEEE East-West Design Test Symposium (EWDTS), Sep. 2015, pp. 1–4.
[22] X. Du, N. Mukherjee, C. Hill, W.-T. Cheng, and S. Reddy, “A field programmable memory BIST architecture supporting algorithms with multiple nested loops,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2006, pp. 287–292.
[23] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59–70, Jan.-Mar. 1999.
[24] P. Jakobsen, J. Dreibelbis, G. Pomichter, D. Anand, J. Barth, M. Nelms, J. Leach, and G. Belansek, “Embedded DRAM built in self test and methodology for test insertion,” in Proc. Int’l Test Conf. (ITC), Nov. 2001, pp. 975–984.
[25] M. Kume, K. Uehara, M. Itakura, and H. Sawamoto, “Programmable at-speed array and functional BIST for embedded DRAM LSI,” in Proc. Int’l Test Conf. (ITC), Oct. 2004, pp. 988–996.
[26] J. E. Barth, D. Anand, S. Burns, J. H. Dreibelbis, J. A. Fifield, K. Gorman, M. Nelms, E. Nelson, A. Paparelli, G. Pomichter, D. E. Pontius, and S. Sliva, “A 500-MHz multi- banked compilable DRAM macro with direct write and programmable pipelining,” IEEE Jour. of Solid-State Circuits, vol. 40, no. 1, pp. 213–222, Jan. 2005.
[27] C.-F. Lin, J.-C. Ou, M.-H. Wang, Y.-S. Ou, and M.-H. Ku, “Single-instruction based programmable memory BIST for testing embedded DRAM,” in IEEE Int’l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, April 2009, pp. 291–294.
[28] K. Gorman, M. Roberge, A. Paparelli, G. Pomichter, S. Sliva, and W. Corbin, “Ad- vancements in at-speed array BIST: multiple improvements,” in Proc. Int’l Test Conf. (ITC), Oct. 2010, Paper 3.1, pp. 1–10.
[29] P. Bernardi, M. Grosso, M. S. Reorda, and Y. Zhang, “A programmable BIST for DRAM testing and diagnosis,” in Proc. Int’l Test Conf. (ITC), Oct. 2010, Paper 15.3, pp. 1–10.
[30] S. Boutobza, M. Nicolaidis, K. M. Lamara, and A. Costa, “Programmable memory BIST,” in Proc. Int’l Test Conf. (ITC), Austin, Nov. 2005, Paper 45.2, pp. 1–10.
[31] C.-C. Yang, J.-F. Li, Y.-C. Yu, K.-T. Wu, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, and Y.-F. Chou, “A hybrid built-in self-test scheme for DRAMs,” in IEEE Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2015, pp. 1–4.
[32] H. Hashimoto, T. Fukushima, K. Lee, M. Koyanagi, and T. Tanaka, “Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system,” in IEEE Int’l 3D Systems Integration Conference (3DIC), San Francisco, Oct. 2013, pp. 1–5.
[33] A.-C. Hsieh and T.-T. Hwang, “TSV redundancy: architecture and design issues in 3-D IC,” IEEE Trans. on VLSI Systems, vol. 20, no. 4, pp. 711–722, Apr. 2012.
[34] M. Laisne, K. Arabi, and T. Petrov, “Systems and methods utilizing redundancy in semiconductor chip interconnects,” US Patent No. 20100060310 A1, Mar. 2010.
[35] G. V. der Plas and et al., “Design issues and considerations for low-cost 3-D TSV IC technology,” IEEE Jour. of Solid-State Circuits, vol. 46, no. 1, pp. 293–307, Jan 2011.
[36] M. Nicolaidis, V. Pasca, and L. Anghel, “Through-silicon-via built-in self-repair for aggressive 3D integration,” in On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International, 2012, pp. 91–96.
[37] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small delay testing for TSVs in 3D ICs,” in Proc. IEEE/ACM Design Automa- tion Conf. (DAC), San Francisco, June 2010, pp. 1031–1036.
[38] C.-C. Chi, C.-W. Wu, M.-J. Wang, and H.-C. Lin, “3D-IC interconnect test, diagnosis, and repair,” in Proc. IEEE VLSI Test Symp. (VTS), 2013, pp. 118–123.
[39] C.-W. Chou, Y.-J. Huang, and J.-F. Li, “A built-in self-repair scheme for 3D RAMs with interdie redundancy,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 4, pp. 572–583, April 2013.
[40] L. Jiang, F. Ye, Q. Xu, K. Chakrabarty, and B. Eklow, “On effective and efficient in- field TSV repair for stacked 3D ICs,” in Proc. IEEE/ACM Design Automation Conf. (DAC), Austin, June 2013, pp. 1–6.
[41] ——, “On effective and efficient in-field TSV repair for stacked 3D ICs,” in Proc. IEEE/ACM Design Automation Conf. (DAC), Austin, June 2013, pp. 1–6.
[42] Y. Zhao, S. Khursheed, and B. Al-Hashimi, “Cost-effective tsv grouping for yield im- provement of 3D-ICs,” in IEEE Asian Test Symp. (ATS), Nov 2011, pp. 201–206.
[43] S. Adham and E. J. Marinissen, “IEEE P1838 web site,” http://grouper.ieee.org/groups /3Dtest/.
[44] K.-T. Wu, J.-F. Li, C.-Y. Lo, J.-S. Lai, D.-M. Kwai, and Y.-F. Chou, “A channel- shareable built-in self-test scheme for multi-channel DRAMs,” in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Jan. 2018, pp. 245–250.
[45] K.-T. Wu, J.-F. Li, Y.-C. Yu, C.-S. Hou, C.-C. Yang, D.-M. Kwai, Y.-F. Chou, and C.- Y. Lo, “Intra-channel reconfigurable interface for TSV and micro bump fault tolerance in 3-D RAMs,” in IEEE Asian Test Symp. (ATS), Nov. 2014, pp. 143–148.
[46] H. M. C. Consortium, “Hybrid memory cube (HMC),” http://www.hybridmemorycube. org/, Apr. 2013.
[47] H.-W. Kim and S. Lee, “Design and implementation of a private and public key crypto processor and its application to a security system,” IEEE Trans. on Consumer Elec- tronics, vol. 50, no. 1, pp. 214–224, Feb. 2004.
[48] M. D. Gomony, B. Akesson, and K. Goossens, “Architecture and optimal configuration of a real-time multi-channel memory controller,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Grenoble, 2013, pp. 1307–1312.
[49] E. Azarkhish, C. Pfister, D. Rossi, I. Loi, and L. Benini, “Logic-base interconnect design for near memory computing in the smart memory cube,” IEEE Trans. on VLSI Systems, vol. 25, no. 1, pp. 210–223, Jan. 2017.
[50] M. A. Breuer and A. D. Friedman, Diagnosis & Reliable Design of Digital Systems. Computer Science Press, 1976.
[51] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Chichester, England: John Wiley & Sons, 1991.
[52] K. P. Parker, “3D-IC defect investigation,” IEEE P1838 Defect Tiger Team, Tech. Rep., July 2012.
[53] S. Kannan, B. Kim, and B. Ahn, “Fault modeling and multi-tone dither scheme for testing 3D TSV defects,” Jour. of Electronic Testing: Theory and Applications, vol. 28, no. 1, pp. 39–51, Feb. 2012.
[54] Y. Chen, D. Niu, Y. Xie, and K. Chakrabarty, “Cost-effective integration of three- dimensional (3D) ICs emphasizing testing cost analysis,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2010, pp. 471–476.
[55] B. Noia and K. Chakrabarty, “Identification of defective TSVs in pre-bond testing of 3D ICs,” Proc. IEEE Asian Test Symp. (ATS), pp. 187–194, Aug. 2011.
[56] F. Ye and K. Chakrabarty, “TSV open defects in 3D integrated circuits: Character- ization, test, and optimal spare allocation,” in Proc. IEEE/ACM Design Automation Conf. (DAC), June. 2012, pp. 1024–1030.
[57] I. Loi, F. Angiolini, S. Fujita, S. Mitra, and L. Benini, “Characterization and imple- mentation of fault-tolerant vertical links for 3-D networks-on-chip,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 1, pp. 124–134, Jan. 2011.

指導教授

李進福(Jin-Fu Li)

審核日期

2023-8-21

推文