新穎極小化高密度三維整體堆疊式1T-nF電流熔絲一次性編程記憶體晶片

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：20

、訪客IP：3.14.253.221

姓名

繆旻倫(Min-Lun Miao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

新穎極小化高密度三維整體堆疊式1T-nF電流熔絲一次性編程記憶體晶片
(Novel Ultra Scaled High-Density 3D Stacking Monolithic 1T-nF Electromigration (eFuse) One-Time Programmable Memory)

相關論文

★ 基於十六奈米鰭式場效電晶體平台實現通道轟擊電離編程機制之低成本高速嵌入式動態隨機存取記憶體	★ 具有通道熱電子注入編程能力的40nm 4kb 1T OTP陣列的設計和實現
★ 通過虛擬源極傳輸模型對16-nm應變矽鰭式場效電晶體低溫準彈道傳輸的電性變化建模	★ 基於閾值電壓電性擾動所實現之高速亂數產生率的40-nm 4T-SRAM真亂數產生器記憶體矩陣晶片
★ 多阻態存取1T1R電阻式記憶體矩陣晶片的三態內容定址記憶體的設計和實現	★ 新穎的多阻態之真亂數產⽣器由 40nm電阻式記憶體陣列實現
★ 40奈米之電阻式記憶體陣列透過啟動/設置/重置操作物理不可複製功能的綜合研究	★ 混和訊號 1.6-3.6GHz 相位旋轉延遲鎖定迴路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2029-1-10以後開放)

摘要(中)

由於物聯網蓬勃發展，市場上各種電子產品為了持久的數據和安全碼存儲，使得一次性編程(OTP)記憶體被加以利用，其存儲的數據在編程後無法更改，研究表明過去十年各種產品中所使用的位元數急遽增加，這導致了晶片設計所需給予OTP記憶體陣列的佈局面積增加，其面積設計問題值得深入研究。
本次設計使用熔絲崩潰的機制，在編程時通過加壓產生大電流通過匯流流經熔絲處，於熔絲處通過電遷移使其組態產生轉變，使熔絲從低阻值~50 Ω轉為高阻值3K~10G Ω從而實現編程，傳統的熔絲選用Poly-Fuse，隨著製成微縮目前以選用Metal-Fuse為多數，選用金屬層來當作熔絲能夠實現3D集成堆疊於MOSFET上方縮小佈局面積的使用。由於熔絲崩潰主要是取決於電遷移的力量，理論上設計熔絲的截面積越小，所需使用的電壓電流以及編程的所需時間也能夠變小，具有隨著製成微縮的能力。目前已發展的eFuse一次性編程記憶體其記憶胞設計皆僅只使用一根熔絲來形成，通常採取1T-1F，意即一個記憶胞僅儲存了一個位元，本計畫提出了創新的1T-nF的eFuse OTP NVM的架構，通過使用多層金屬層來做為熔絲，在編程時指定目標金屬層來流經大電流，相比於傳統的1T-1F架構，本次研究設計之1T-nF架構在一個記憶胞能夠儲存n個位元，大幅縮小了佈局面積。
本研究設計eFuse OTP NVM的Bit Cell面積僅有0.447µm^2，編程電壓僅為1.8V，遠低於反熔絲崩潰所需之編程電壓4~5V，與其所運用周邊電路進行讀取速度15ns，且金屬熔絲經過讀取干擾測試電熔絲重複讀取〖10〗^12次與資料保存可靠度測試於200°C烘烤一個月皆未發現金屬熔絲發生阻態的改變，此設計可有效縮小目前eFuse OTP NVM陣列所占面積過大之問題。

摘要(英)

Due to the flourishing development of the Internet of Things (IoT), various electronic products in the market are utilizing One-Time Programmable (OTP) memory for persistent data and security code storage. The stored data in OTP memory cannot be altered after programming. Research indicates a significant increase in the number of bits used in various products over the past decade, leading to an increased layout area for OTP memory arrays in chip design, prompting the need for in-depth investigation into area design issues.
In this thesis, a mechanism involving the breakdown of fuses is employed. During programming, a high current is generated by applying pressure, flowing through the fuse location. Electromigration at the fuse location induces a configuration change, transforming the fuse from a low resistance value (~50 Ω) to a high resistance value (3K~10 GΩ), achieving the programming functionality. Traditional fuses used Poly-Fuse, but currently, Metal-Fuse is preferred, utilizing a metal layer for 3D integration stacked above MOSFET to reduce layout area.
As fuse breakdown primarily depends on the force of electromigration, theoretically, designing a smaller cross-sectional area for the fuse reduces the required voltage, current, and programming time, demonstrating scalability with technology scaling. Existing eFuse single programmable memory cells typically use only one fuse to form a memory cell, usually adopting a 1T-1F configuration, meaning one memory cell stores one bit. This project proposes an innovative 1T-nF eFuse OTP NVM architecture, utilizing different metal layers as fuses. During programming, a target metal layer is specified to carry a high current. Compared to the traditional 1T-1F structure, the 1T-nF architecture in this study allows one memory cell to store n bits, significantly reducing the layout area.
The bit cell area of the designed eFuse OTP NVM in this research is only 0.447µm^2, with a programming voltage of 1.8V, much lower than the 4-5V required for anti-fuse breakdown. It achieves a reading speed of 15ns with peripheral circuits and undergoes interference testing, repeated fuse reading of 〖10〗^12 times, and data retention reliability testing at 200°C for a month without observing changes in the metal fuse resistance state. This design effectively addresses the issue of the excessive footprint of current eFuse OTP NVM arrays.

關鍵字(中)

★ 一次性編程記憶體
★ 高密度
★ 多位元存儲

關鍵字(英)

★ One-Time Programmable Memory
★ High-Density
★ Multi-bit Storage

論文目次

摘要 I
Abstract II
致謝 IV
圖目錄 VII
表目錄 X
一、導論 1
1.1背景 1
1.2研究動機 2
1.3論文架構 3
二、一次性可編程記憶體發展與物理機制 5
2.1一次性可編程記憶體發展 5
2.1.1電熔絲記憶體元件 (eFuse) 5
2.1.2反熔絲記憶體元件 (Anti-Fuse) 6
2.2電熔絲記憶體編程物理機制 6
2.2.1電遷移（Electromigration） 6
2.2.2熱遷移與焦耳熱效應 7
2.2.3平均失效時間（MTTF） 8
2.3小結 8
三、 1T-nF電熔絲記憶體單元與陣列 15
3.1傳統1T-1F電熔絲記憶體單元 15
3.2 1T-nF電熔絲記憶體單元 15
3.2.1 1T-nF介紹 15
3.2.2 1T-2F、1T-4F組成之記憶體單元與陣列 16
3.3 1T-1F與1T-nF架構之迴路差異分析 16
四、 1T-nF電熔絲記憶體陣列模擬與周邊電路 24
4.1 電流感測放大器 24
4.2 邏輯控制開關電路 24
4.3 正電壓位準偏移器 25
4.4 1T-nF電熔絲記憶體介紹 25
4.5 1T-nF電熔絲記憶體陣列 25
4.6 1T-nF電熔絲記憶體操作 26
4.6.1 資料編程 (Program) 26
4.6.2 資料讀取 (Read) 28
4.7 1T-nF電熔絲記憶體功耗、面積 29
五、電熔絲量測結果 55
5.1 實驗設置 55
5.2 編程Shmoo圖 55
5.3 讀取電流分布 (Current Distribution) 56
5.4 讀取干擾測試 (Read Disturb) 56
5.5 資料保存可靠度測試 (Retention) 56
六、結論 64
參考文獻 69

參考文獻

[1] Z. Chen, S. H. Kulkarni, V. E. Dorgan, S. M. Rajarshi, L. Jiang and U. Bhattacharya, "A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming," in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 933-939, 2017 doi: 10.1109/JSSC.2016.2641955.
[2] J. Raszka, M. Advani, V. Tiwari, L. Varisco, N. D. Hacobian, A. Mittal, M. Han, A. Shirdel, A. Shubat , "Embedded flash memory for security applications in a 0.13um CMOS logic process" IEEE International Solid-State Circuits Conference, 2004, pp. 46-512 Vol.1 doi: 10.1109/ISSCC.2004.1332586.
[3] J. Rosenberg, "Embedded flash on a CMOS logic process enables secure hardware encryption for deep submicron designs," Symposium Non-Volatile Memory Technology 2005., pp.19-21. doi: 10.1109/NVMT.2005.1541381.
[4] V. Srinivasan, G. J. Serrano, J. Gray and P. Hasler, "A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation," in IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 280-291, Feb. 2007 doi: 10.1109/JSSC.2006.889365.
[5] W. C. Wang, C. C. Chuang, C. W. Chang, E. R. Hsieh, H. W. Chen and S. S. Chung, "A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password," 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 31.6.1-31.6. doi: 10.1109/IEDM13553.2020.9371898.
[6] H.K. Cha, I. Yun, J. Kim, B. C. So, K. Chun, I. Nam, K. Lee, "A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller," in IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2115-2124, 2006. doi: 10.1109/JSSC.2006.880603.
[7] J. Peng, G. Rosendale, M. Fliesler, D. Fong, J. Wang, C. Ng, Z. Liu, H. Luan, "A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology," 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop, 2006, pp. 24-26 doi: 10.1109/.2006.1629479.
[8] Jeong-Ho Kim, Du-Hwi Kim, Liyan Jin, Pan-Bong Ha, and Young-Hee Kim, "Design of 1-Kb eFuse OTP Memory IP with Reliability Considered," JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.11, NO.2, JUNE, 2011 pp. 88-94, doi:10.5573/JSTS.2011.11.2.088
[9] Mohsen Alavi , Mark Bohr, Jeff Hicks, Martin Denham, Allen Cassens, Dave Douglas, Min-Chun Tsai, “A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process,” International Electron Devices Meeting. IEDM Technical Digest, 1997, pp. 855-858, doi: 10.1109/IEDM.1997.650515.
[10] Greg Uhlmann; Tony Aipperspach; Toshiaki Kirihata; Yan Zun Li; Chris Paone; Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian Iyer;, “A commercial field-programmable dense eFUSE array memory with 99.999% sense yield for 45 nm SOI CMOS,” 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, pp. 406-407, doi: 10.1109/ISSCC.2008.4523229.
[11] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J.He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," 2007 IEEE International Electron Devices Meeting, 2007, pp. 247-250, doi: 10.1109/IEDM.2007.4418914.
[12] S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C. H. Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He, R. Heussner “A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171 µm^2 SRAM cell size in a 291 Mb array,” 2008 IEEE International Electron Devices Meeting, 2008, pp. 1-3, doi: 10.1109/IEDM.2008.4796777.
[13] Woan Yun Hsiao, Chin Yu Mei, Wen Chao Shen, Tzong Sheng Chang, Yue Der Chih, Ya-Chin King, Chrong Jung Lin, "A high density Twin-Gate OTP cell in pure 28nm CMOS process," Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, pp. 1-2 doi: 10.1109/VLSI-TSA.2014.6839664.
[14] Y. -Z. Chen, J. E. Yuan, C. J. Lin and Y. -C. King, "Multilevel Anti-Fuse Cells by Progressive Rupturing of the High- κ Gate Dielectric in FinFET Technologies," in IEEE Electron Device Letters, vol. 37, no. 9, pp. 1120-1122, Sept. 2016, doi: 10.1109/LED.2016.2591581.
[15] J. Kim and K. Lee, "Three-transistor one-time programmable (OTP) ROM cell array using standard CMOS gate oxide antifuse", IEEE Electron Device Letters., vol. 24, no. 9, pp. 589-591, Sep. 2003. doi: 10.1109/LED.2003.815429.
[16] S. -Y. Chou, Y. -S. Chen, J. -H. Chang, Y. -D. Chih and T. -Y. J. Chang, "11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme," 2017 IEEE International Solid-State Circuits Conference (ISSCC) 2017, pp. 200-201, doi: 10.1109/ISSCC.2017.7870330.
[17] Guangyan Zhao, Yong Zhao and W. T. K. Chien, "Reliability investigations on the programming currents of 28nm metal e-Fuse," 2017 China Semiconductor Technology International Conference (CSTIC), 2017, pp. 1-3 doi: 10.1109/CSTIC.2017.7919737.
[18] Kuei-Sheng Wu, Chang-Chien Wong, Sinclair Chi, Ching-Hsiang Tseng, Purple Huang, Devon Huang, and Titan Su, “The improvement of electrical programming fuse with silicide-block dielectric film in 40nm CMOS Technology,” 2010 IEEE International Interconnect Technology Conference, 2010, pp. 1-3. doi: 10.1109/IITC.2010.5510461.
[19] I. V. Ermakov, A. Y. Losevskoy, A. V. Nuykin, N. A. Shelepin and A. S. Kravtsov, "Design and Study of a 65 Kb AntiFuse OTP ROM in a Standard 0.18 um CMOS Process," 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering , 2020, pp. 112-115 doi: 10.1109/EIConRus49466.2020.9038926.
[20] Chiu-Wang Lien; Haw-Yun Wu; Cheng-Wei Tsai; Chen-Mei Huang; Yue-Der Chih; Te-Liang Lee; Chrong Jung Lin., "A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process," in IEEE Transactions on Electron Devices, vol. 59, no. 7, pp. 1899-1905, July 2012 doi: 10.1109/TED.2012.2196518.
[21] F. Husain, B. Iqbal and A. Grover, "A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology," 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, pp. 76-81, doi: 10.1109/VLSID51830.2021.00018.
[22] P. Liu, X. Wang, D. Wu, Z. Zhang and L. Pan, "A novel high-speed and low-power negative voltage level shifter for low voltage applications," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010, pp. 601-604 doi: 10.1109/ISCAS.2010.5537521.
[23] S. H. Kulkarni, Z. Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya and K. Zhang, "Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process," 2015 Symposium on VLSI Technology (VLSI Technology), Kyoto, Japan, 2015, pp. C174-C175 doi: 10.1109/VLSIT.2015.7223645.
[24] M. -C. Hsieh, Y. -C. Lin, Y. -W. Chin, T. -S. Chang, Y. -C. King and C. -J. Lin, "Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology," in IEEE Electron Device Letters, vol. 34, no. 9, pp. 1088-1090, Sept. 2013 doi: 10.1109/LED.2013.2272475.
[25] S. H. Kulkarni, Z. Chen, J. He, L. Jiang, M. B. Pedersen and K. Zhang, "A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 863-868, April 2010, doi: 10.1109/JSSC.2010.2040115.
[26] Greg Uhlmann, Tony Aipperspach, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian Iyer "A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Paper, 2008, pp. 406-407, doi: 10.1109/ISSCC.2008.4523229.
[27] S. H. Kulkarni, Sangwoo Pae, Zhanping Chen, Walid Hafez, Brian Pedersen, Anisur Rahman, Tom Tong, Uddalak Bhattacharya, Chia-Hong Jan, Kevin Zhang., "A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell," 2012 Symposium on VLSI Technology (VLSIT), 2012, pp. 79-80, doi: 10.1109/VLSIT.2012.6242470.
[28] Yi-Hung Tsai, Hsin-Ming Chen, Hsin-Yi Chiu, Hung-Sheng Shih, Han-Chao Lai, Ya-Chin King, Chrong Jung Lin, "45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process," 2007 IEEE International Electron Devices Meeting, Washington, DC, USA, 2007, pp. 95-98, doi: 10.1109/IEDM.2007.4418872.
[29] E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen and S. S. Chung, "The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond," 2019 Symposium on VLSI Circuits, 2019, pp. C208-C209, doi: 10.23919/VLSIC.2019.8778094.
[30] S. -H. Song, J. Kim and C. H. Kim, "Program/erase speed, endurance, retention, and disturbance characteristics of single-poly embedded flash cells," 2013 IEEE International Reliability Physics Symposium (IRPS), 2013, pp. MY.4.1-MY.4.6, doi: 10.1109/IRPS.2013.6532095.

指導教授

謝易叡(E-Ray Hsieh)

審核日期

2024-1-11

推文