應用於SATA-III規格之可控頻率調變曲線的展頻時脈產生器

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姓名

林藝真(Yi-Jhen Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於SATA-III規格之可控頻率調變曲線的展頻時脈產生器
(A SATA-III Spread-Spectrum Clock Generator with Controllable Frequency Modulation Profile)

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至系統瀏覽論文 (2029-1-19以後開放)

摘要(中)

為了提高電子產品的操作頻率，且電路操作在準確的頻率時，時脈訊號的能量會被集中在單一頻率，這表示著時脈訊號包含了許多的高次諧波能量。這些高頻訊號對於周邊的電路而言，無疑是形成了電磁干擾( EMI )，並可能導致電路的操作異常，因此電磁波干擾抑制技術，明顯成為電子產品必須解決的根本問題。本論文提出一個應用於SATA-III規格與可控頻率調變曲線的展頻時脈產生器(SSCG)，在不改變展頻調變量與調變頻率的情況下，改變頻率調變曲線，來實現電磁干擾的抑制，並利用高解析度的相位切換除頻器，讓頻率變化的幅度降低，以達到較低的系統抖動表現。
本論文使用TSMC 90 nm CMOS製程實現，電路操作電壓為1.0 V，中心頻率為6 GHz，調變波型之調變頻率為31.25 kHz，向下展頻4166 ppm。展頻機制開啟後，根據頻率調變曲線的變化，電磁干擾抑制量會從24 dB提升到26 dB。整體晶片面積為0.96 mm2，核心電路面積為0.053 mm2，整體電路的功率消耗為24.9 mW，未開啟與開啟展頻模式的方均根抖動分別是0.11 ps 與 0.23 ps，未開啟與開啟展頻模式的峰對峰值抖動分別是1.13 ps 與 1.50 ps。

摘要(英)

To enhance the operating frequency of electronic products, when the circuit operates at an accurate frequency, the energy of the clock signal will be concentrated at a single frequency. This indicates that the clock signal contains a significant amount of high-order harmonic energy. For peripheral circuits, these high-frequency signals undoubtedly generate electromagnetic interference (EMI), potentially leading to circuit malfunctions. Therefore, electromagnetic interference suppression techniques have become a fundamental issue that electronic products must address.
This thesis proposes a Spread Spectrum Clock Generator (SSCG) applied to the SATA-III specification with a controllable frequency modulation profile. Without changing the spreading modulation amount and modulation frequency, the paper modifies the frequency modulation curve to achieve EMI suppression. By using a high-resolution phase-switching divider, the magnitude of frequency variation is reduced to achieve lower system jitter performance.
This work is implemented using the TSMC 90 nm CMOS process, operating at a voltage of 1.0 V, with a central frequency of 6 GHz. The modulation frequency of the modulation waveform is 31.25 kHz, and the downward spread is 4166 ppm. When the spreading mechanism is activated, the EMI suppression increases from 24 dB to 26 dB due to changes in the frequency modulation curve. The overall chip area is 0.96 mm2, with a core circuit area of 0.053 mm2. The power consumption of the entire circuit is 24.9 mW. The root mean square (RMS) jitter in both deactivated and activated spread modes is 0.11 ps and 0.23 ps, respectively. The peak-to-peak jitter values in both modes are 1.13 ps and 1.50 ps, respectively.

關鍵字(中)

★ 展頻時脈產生器
★ 鎖相迴路
★ Delta-Sigma調變
★ 鋸齒波
★ 可控頻率調變曲線

關鍵字(英)

★ Spread spectrum clock generator
★ Phase locked loop
★ Delta-Sigma modulation
★ Sawtooth
★ controllable modulation profile

論文目次

摘要i
Abstractii
目錄v
圖目錄viii
表目錄xi
第一章緒論1
1.1 研究動機1
1.2 論文架構2
第二章展頻時脈產生器先前技術探討3
2.1 電磁干擾來源與解決辦法3
2.2 展頻時脈概念 3
2.2.1 頻率調變方向4
2.2.2 頻率調變類型5
2.3 展頻時脈產生器先前技術探討6
2.3.1 直接調變(Direct Modulation)[9]6
2.3.2 相位調變(Phase Modulation)[20]8
2.3.3 Delta-Sigma調變(Delta-Sigma Modulation)[32]9
2.3.4 比較與討論11
第三章可控頻率調變曲線之展頻時脈產生器12
3.1 SATA-III規格簡介12
3.2 設計流程13
3.3 設計概念14
3.4 電路架構及操作16
3.4.1 三角積分調變器17
3.4.2 非整數頻率除頻器24
3.4.3 三角波產生器26
3.4.4 鎖相迴路系統分析30
3.4.5 行為模擬35
第四章子電路架構設計考量與模擬37
4.1 鎖相迴路之子電路設計37
4.1.1 相位頻率偵測器37
4.1.2 電荷幫浦39
4.1.2.1 電荷分享41
4.1.2.2 時脈饋入42
4.1.3 迴路濾波器 43
4.1.4 電壓控制振盪器44
4.1.5 多模數除頻器47
4.2 展頻之子電路設計51
4.2.1 除50除頻器52
4.2.2 上/下數控制電路53
4.2.3 上/下數計數器54
4.2.3.1 三角波產生器的應用54
4.2.3.2 DSM的後端電路的應用55
4.2.4 斜率控制器55
4.3 模擬結果58
4.3.1 佈局前模擬59
4.3.1.1 鎖相迴路59
4.3.1.2 展頻時脈產生器60
4.3.2 佈局後模擬63
4.3.2.1 鎖相迴路63
4.3.2.2 展頻時脈產生器64
4.3.3 結果整理67
4.4 規格比較表68
第五章晶片佈局與量測規劃70
5.1 電路佈局70
5.1.1 晶片封裝71
5.1.2 電源佈局與規劃73
5.2 量測考量74
5.2.1 量測環境74
5.2.2 低頻輸入緩衝器75
5.2.3 低頻輸出緩衝器76
5.2.4 高頻輸出緩衝器77
第六章結論與未來研究方向78
6.1 結論78
6.2 未來研究方向79
參考文獻80

參考文獻

[1]High-Definition Multimedia Interface Specification, Version 2.0, HDMI, 2013
[2]DisplayPort (DP) Standard, Version 2.0, VESA, 2019
[3]Universal Serial Bus 4 Specification, Version, USB-IF, 2019.
[4]Serial ATA International Organization, Serial ATA Revision 3.2, SATA-IO, 2013.
[5]PCI Express® Base Specification, Revision 4.0 Version 0.7, PCI-SIG, 2016.
[6]T. Sudo, H. Sasaki, N. Masuda and J. L. Drewniak “Electromagnetic Interference (EMI) of System-on-Package (SOP),” IEEE Trans. On Advanced Packaging, Vol. 27, no. 2, pp. 304-314, May 2004.
[7]I.-H. Hua “The Design and Implementation of 66/133/266MHz Spread Spectrum Clock Generators,” NTU MS. Thesis, 2002.
[8]A. Shoval, W. Martin and D. A. Johns “A 100 Mb/s BiCMOS Adaptive Pulse-Shaping Filter,” IEEE J. on Selected Areas in Communication, Vol. 13, pp. 1692-1702, Dec. 1995.
[9]Hsiang-Hui Chang, I-Hui Hua and Shen-Iuan Liu, "A spread-spectrum clock generator with triangular modulation," in IEEE Journal of Solid-State Circuits, vol. 38, no. 4, pp. 673-676, April 2003.
[10]Hyung-Rok Lee, Ook Kim, Gijung Ahn and Deog-Kyoon Jeong, "A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18 μm CMOS," ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., San Francisco, CA, USA, 2005, pp. 162-590 Vol. 1.
[11]S. Damphousse, K. Ouici, A. Rizki and M. Mallinson, "All Digital Spread Spectrum Clock Generator for EMI Reduction," in IEEE Journal of Solid-State Circuits, vol. 42, no. 1, pp. 145-150, Jan. 2007.
[12]D. -S. Shen and S. -I. Liu, "A Low-Jitter Spread Spectrum Clock Generator Using FDMP," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 11, pp. 979-983, Nov. 2007.
[13]F. Pareschi, G. Setti and R. Rovatti, "A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation," 2008 IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2008, pp. 451-454.
[14]F. Pareschi, G. Setti and R. Rovatti, "A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2577-2587, Oct. 2010.
[15]Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim and Chulwoo Kim, "A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation," 2008 IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, 2008, pp. 455-458.
[16]C. -Y. Yang, C. -H. Chang, and W. -G. Wong,“A 3.2-GHz down-spread spectrum clock generator using a nested fractional topology,”IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. 91, no. 2, pp. 497–503, Feb. 2008.
[17]W. Lee and S. Cho, "A 900 MHz 2.2 mW spread spectrum clock generator based on direct frequency synthesis and harmonic injection locking," 2009 International SoC Design Conference (ISOCC), Busan, Korea (South), 2009, pp. 524-527.
[18]C. -Y. Yang, C. -H. Chang and W. -G. Wong, "A ΔΣ PLL-Based Spread-Spectrum Clock Generator With a Ditherless Fractional Topology," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 1, pp. 51-59, Jan. 2009.
[19]S. -Y. Lin and S. -I. Liu, "A 1.5 GHz All-Digital Spread-Spectrum Clock Generator," in IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3111-3119, Nov. 2009.
[20]K. -H. Cheng, C. -L. Hung and C. -H. Chang, "A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique," in IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1198-1213, May 2011.
[21]W. -Y. Lee and L. -S. Kim, "A Spread Spectrum Clock Generator for DisplayPort Main Link," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 6, pp. 361-365, June 2011.
[22]D. Sheng, C. -C. Chung and C. -Y. Lee, "A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113-1117, June 2011.
[23]Seung-Wook Oh, Hyung-Min Park, Joon-Hyup Seo, Jae-Young Jang, Gi-Yeol Bae and Jin-Ku Kang, "A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS," 2012 International SoC Design Conference (ISOCC), Jeju Island, 2012, pp. 423-426.
[24]Young-Ho Choi, Jae-Yoon Sim and Hong-June Park, "A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator," 2012 International SoC Design Conference (ISOCC), Jeju Island, 2012, pp. 68-71.
[25]Sewook Hwang, Minyoung Song, Young-Ho Kwak, Inhwa Jung and Chulwoo Kim, "A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile," in IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1199-1208, May 2012.
[26]I. -T. Lee, S. -H. Ku and S. -I. Liu, "An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 11, pp. 2813-2822, Nov. 2013.
[27]M. Song, S. Ahn, I. Jung, Y. Kim and C. Kim, "Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 7, pp. 1234-1245, July 2013.
[28]I. -H. Chung, K. -S. Kwak, J. -H. Ra, S. -K. Hong and O. -K. Kwon, "A spread spectrum clock generator with controllable frequency modulation profile," 2013 International SoC Design Conference (ISOCC), Busan, Korea (South), 2013, pp. 123-126.
[29]H. Ryu, S. Park, E. -T. Sung, S. -G. Lee and D. Baek, "A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices," in IEEE Transactions on Electromagnetic Compatibility, vol. 57, no. 6, pp. 1447-1456, Dec. 2015.
[30]C. -C. Chung,D.Sheng,and W. -D.Ho, “A low-cost low-power all-digital spread-spectrum clock generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983–987, May 2015.
[31]S. -G. Bae, G. Kim and C. Kim, "A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 10, pp. 1132-1136, Oct. 2017.
[32]J. Jun, S. -G. Bae, Y. Lee and C. Kim, "A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 11, pp. 1509-1513, Nov. 2018.
[33]S. -G. Bae, S. Hwang, J. Song, Y. Lee and C. Kim, "A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 192-196, Feb. 2019.
[34]X. Guan, T. Yang and F. Tang, "A 5-GHz Phase Compensation Spread Spectrum Clock Generator for High Speed SerDes Application," 2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM), Nanjing, China, 2020, pp. 293-297.
[35]H. Sun, K. Sobue, K. Hamashita, T. Anand and U. -K. Moon, "A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator," in IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 426-438, Feb. 2020.
[36]劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006.
[37]傅翔宥, “使用片段線性調變與製程補償技術之六十億赫茲展頻時脈產生器,“碩士論文, 國立台北大學, 2016.
[38]陳永旭, “使用真除數與多頻帶校正之SATA-III展頻時脈展生器,“碩士論文, 國立台北大學, 2020.
[39]A. M. Fahim, “A compact, low-power low-jitter digital PLL,” in Proc. IEEE European Solid-State Circuit Conference, Sept. 2003, pp. 101–104.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-1-17

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