具自適應迴路增益控制器之 5 Gbps 相位內插式 時脈與資料回復電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：102

、訪客IP：3.145.56.203

姓名

廖品媗(Pin-Hsuan Liao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具自適應迴路增益控制器之 5 Gbps 相位內插式時脈與資料回復電路
(A 5 Gbps PI-based Clock and Data Recovery with Adaptive Loop Gain Controller)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2029-1-19以後開放)

摘要(中)

近年來，隨著半導體產業的迅速發展，產品應用需要更高的資料傳輸頻寬，高速串列傳輸技術成為現在資料傳輸的主流。在串列傳輸系統中，接收端需要使用時脈與資料回復電路來重新調整輸入資料的時脈，以確保正確的資料還原。然而，系統中可能存在各種雜訊和訊號衰減，導致誤碼率上升，因此提升抖動容忍度、減少誤碼率成為時脈與資料回復電路中的設計目標。

本論文根據 USB 3.2 gen 1 規格實現一個具自適應迴路增益控制器之 5 Gbps 相位內插式時脈與資料回復電路。透過觀察相位旋轉器旋轉狀況，自適應迴路增益控制器偵測輸入資料的抖動頻率資訊，切換資料回復迴路的迴路增益，以達到在不同的抖動頻率下，優化系統的產生的抖動，提升整體電路的抖動容忍度，降低誤碼率。自適應迴路增益改善了 132% 的低頻抖動容忍度和 17% 高頻抖動容忍度。本論文使用用 TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程來實現，電路操作電壓為 1 V，晶片面積為 1.49 mm2，核心電路面積為 0.066 mm2，輸入資料速率為 5 Gbps 時，還原時脈的峰對峰值抖動為 14.7 pspp，方均根值抖動為 3.46 psrms，消耗功率為 31.04 mW。

摘要(英)

In recent years, with the rapid development of the semiconductor industry, products require higher data transmission bandwidth, and high-speed serial transmission technology has become the mainstream for data transmission. In serial transmission systems, the RX needs to use clock and data recovery circuits (CDR) to readjust the input data clock to ensure accurate data recovery. However, various noise and signal attenuation may exist in the system, leading to an increase in error rates. Therefore, improving jitter tolerance (JTOL) and reducing Bit-Error-Rate (BER) have become design goals in clock and data recovery circuits.

This paper presents the implementation of a 5 Gbps phase-interpolator based clock and data recovery circuit with an adaptive loop gain controller (ALGC) based on the USB 3.2 Gen 1 specification.The adaptive loop gain controller detects the jitter frequency information of the input data, switches the loop gain of the data recovery loop, and optimizes JTOL under different jitter frequencies. This enhances the overall circuit′s jitter tolerance and reduces error rates. The adaptive loop gain improves low-frequency jitter tolerance by 132% and high-frequency jitter tolerance by 17%. The circuit is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process, operates at 1 V, with a chip area of 1.49 mm², a core circuit area of 0.066 mm². At a data rate of 5 Gbps, the peak-to-peak jitter of the recovered clock is 14.7 pspp, the root mean square jitter is 3.46 psrms, and the power consumption is 31.04 mW.

關鍵字(中)

★ 時脈與資料回復電路
★ 抖動容忍度

關鍵字(英)

★ Clock and Data Recovery
★ CDR
★ Jitter tolerance

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章高速串列傳輸之訊號完整性 4
2.1 隨機二位元資料 4
2.1.1 資料型態 4
2.1.2 資料特性 5
2.1.3 資料編碼形式 6
2.2 抖動介紹 7
2.2.1 定量性抖動 (Deterministic Jitter, DJ) 8
2.2.2 隨機性抖動 (Random Jitter, RJ) 11
2.3 抖動量測方法 12
2.3.1 時間間隔誤差 (Time Interval Error, TIE) 13
2.3.2 週期抖動 (Period Jitter) 13
2.3.3 循環抖動 (Cycle-to-Cycle Jitter) 13
2.4 眼圖分析 14
2.5 誤碼率 (Bit Error Rate, BER) 15
第3章時脈與資料回復電路背景介紹 18
3.1 時脈與資料回復電路簡介 18
3.1.1 相位偵測器型態 19
3.1.2 相位偵測器取樣速率 20
3.1.3 抖動容忍度 (Jitter Tolerance, JTOL) 21
3.1.4 抖動轉移函數 (Jitter Transfer, JTF) 22
3.2 時脈與資料回復電路相關設計 23
3.2.1 鎖相迴路式時脈與資料回復電路 (PLL-based CDR) 23
3.2.2 混合鎖相迴路及延遲鎖相迴路式時脈與資料回復電路 (D/PLL CDR) 24
3.2.3 突發模式時脈與資料回復電路 (Burst mode CDR) 25
3.2.4 超取樣式時脈與資料回復電路 (Oversampling CDR) 26
3.2.5 相位內插器式時脈與資料回復電路 27
3.3 自適應時脈與資料回復電路相關設計 28
3.3.1 自適應解析度控制之相位內插式時脈與資料回復電路 28
3.3.2 自適應迴路頻寬之相位內插式時脈與資料回復電路 29
3.3.3 自適應迴路增益之時脈與資料回復電路 30
3.4 比較與討論 31
第4章具自適應迴路增益控制器之相位內插式時脈與資料回復電路設計與實現 33
4.1 電路架構 33
4.2 鎖相迴路 35
4.2.1 鎖相迴路系統分析 36
4.2.2 相位頻率偵測器 (Phase Frequency Detector, PFD) 38
4.2.3 充電幫浦 (Charge Pump, CP) 40
4.2.4 壓控震盪器 (Voltage Controlled Oscillator, VCO) 41
4.2.5 除頻器(Divider) 43
4.3 資料回復迴路 44
4.3.1 資料回復迴路系統分析 45
摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 xi
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第2章高速串列傳輸之訊號完整性 4
2.1 隨機二位元資料 4
2.1.1 資料型態 4
2.1.2 資料特性 5
2.1.3 資料編碼形式 6
2.2 抖動介紹 7
2.2.1 定量性抖動 (Deterministic Jitter, DJ) 8
2.2.2 隨機性抖動 (Random Jitter, RJ) 11
2.3 抖動量測方法 12
2.3.1 時間間隔誤差 (Time Interval Error, TIE) 13
2.3.2 週期抖動 (Period Jitter) 13
2.3.3 循環抖動 (Cycle-to-Cycle Jitter) 13
2.4 眼圖分析 14
2.5 誤碼率 (Bit Error Rate, BER) 15
第3章時脈與資料回復電路背景介紹 18
3.1 時脈與資料回復電路簡介 18
3.1.1 相位偵測器型態 19
3.1.2 相位偵測器取樣速率 20
3.1.3 抖動容忍度 (Jitter Tolerance, JTOL) 21
3.1.4 抖動轉移函數 (Jitter Transfer, JTF) 22
3.2 時脈與資料回復電路相關設計 23
3.2.1 鎖相迴路式時脈與資料回復電路 (PLL-based CDR) 23
3.2.2 混合鎖相迴路及延遲鎖相迴路式時脈與資料回復電路 (D/PLL CDR) 24
3.2.3 突發模式時脈與資料回復電路 (Burst mode CDR) 25
3.2.4 超取樣式時脈與資料回復電路 (Oversampling CDR) 26
3.2.5 相位內插器式時脈與資料回復電路 27
3.3 自適應時脈與資料回復電路相關設計 28
3.3.1 自適應解析度控制之相位內插式時脈與資料回復電路 28
3.3.2 自適應迴路頻寬之相位內插式時脈與資料回復電路 29
3.3.3 自適應迴路增益之時脈與資料回復電路 30
3.4 比較與討論 31
第4章具自適應迴路增益控制器之相位內插式時脈與資料回復電路設計與實現 33
4.1 電路架構 33
4.2 鎖相迴路 35
4.2.1 鎖相迴路系統分析 36
4.2.2 相位頻率偵測器 (Phase Frequency Detector, PFD) 38
4.2.3 充電幫浦 (Charge Pump, CP) 40
4.2.4 壓控震盪器 (Voltage Controlled Oscillator, VCO) 41
4.2.5 除頻器(Divider) 43
4.3 資料回復迴路 44
4.3.1 資料回復迴路系統分析 45
4.3.2 自適應迴路增益技術操作說明 47
4.3.3 自適應迴路增益控制器 (Adaptive Loop Gain Controller, ALGC) 50
4.3.4 二進位相位偵測器 (Bang-bang Phase Detector, BBPD) 52
4.3.5 解串列器/多數投票機制電路 (Deserializer/Majority Voter, Des/MV) 54
4.3.6 相位旋轉器 (Phase Rotator, PR) 56
4.3.7 相位選擇器 (Phase Selector, PS) 57
4.3.8 相位內插器 (Phase Interpolator, PI) 58
4.4 模擬結果 59
4.4.1 佈局前模擬 60
4.4.2 佈局後模擬 63
第5章晶片佈局與量測 67
5.1 電路佈局 67
5.1.1 晶片封裝 68
5.1.2 晶片電源佈局與規劃 70
5.2 量測考量 71
5.2.1 量測環境 71
5.2.2 低頻輸入緩衝器 72
5.2.3 高頻輸入緩衝器 73
5.2.4 高頻輸出緩衝器 74
5.3 規格比較表 75
第6章結論 77
6.1 結論 77
6.2 未來研究方向 78
參考文獻 79

參考文獻

[1] DisplayPort (DP) Standard, Version 2.0, VESA, 2019
[2] High-Definition Multimedia Interface Specification, Version 2.0, HDMI, 2013
[3] PCI Express®Base Specification, Revision 2.1, PCI-SIG, 2010.
[4] Serial ATA International Organization, Serial ATA Revision 3.0, SATA-IO, 2009.
[5] Universal Serial Bus Specification, Revision 3.1, USB-IO, 2013
[6] 孫世洋 , “以符碼間干擾技術實現自適應等化器之 5 Gbps 半速率時脈與資料回復
電路碩士論文 , 國立中央大學 , 2016.
[7] B. Razavi, “Design of Integrated Circuits for Optical Communications ” McGraw-Hill,2003.
[8] A. X. Widmer, and P. A. Franaszek ”A DC-balanced, partitioned-block, 8b/10b ” IBM J. Res and Develop., vol. 27, pp. 440–451, Sep. 1983.
[9] Tektronix, “數位示波器的應用抖動 (jitter)測量 ”.
[10] Maxim, “Choosing AC-Coupling Capacitors,” Application Note: HFAN-1.1, 2000.
[11] N. Radhakrishnan, B. Achkir, J. Fan and J. L. Drewniak, “Stressed jitter analysis for physical link characterization,” in Proc. IEEE International Symposium on Electromagnetic Compatibility, Feb. 2010, pp. 568-572.
[12] Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[13] B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed. New York, NY, USA:McGraw-Hill, 2017.
[14] R. Sarpeshkar, T. Delbruck and C. A. Mead, “White noise in MOS transistors and resistors,”IEEE Circuits and Devices Magazine, vol. 9, no. 6, pp. 23-29, Nov. 1993.
[15] Tektronix, “Understanding and characterizing timing jitter”.
[16] Altera Corporation, “Deterministic Jitter (DJ) Definition and Measurement,” 2009.
[17] SHF Communication Technologies AG, “Application note AN-jitter-1-jitter analysisusing SHF 10000 series bit error rate testers,” 2005.
[18] Maxim, “Optical receiver performance evaluation”.
[19] 劉深淵 , 楊清淵 , 鎖相迴路 , 滄海書局 , 2006.
[20] R. C. Walker and B. Razavi, “Designing bang-bang PLLs for clock and data recovery inserial data transmission systems,” Proc. High-Performance Systems, Feb. 2003, pp.34-45.
[21] J. Lee, K. S. Kundert and B. Razavi, “Analysis and modeling of bang-bang clock and datarecovery circuits,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580,Sept. 2004
[22] T. Lee, Y. -H. Kim and L. -S. Kim, “A 5-Gb/s digital clock and data recovery circuit withreduced DCO supply noise sensitivity utilizing coupling network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 1, pp. 380-384, Jan. 2017.
[23] X. Ge, Y. Chen, X. Zhao, P. -I. Mak and R. P. Martins, “Analysis and verification of jitterin bang-bang clock and data recovery circuit with a second-order loop filter,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 10, pp. 2223- 2236, Oct. 2019.
[24] T. H. Lee and J. F. Bulzacchelli, “A 155 MHz clock recovery delay- and phase-locked loop,” IEEE International Solid-State Circuits Conference Digest of Technical Papers,Dec. 1992, pp. 160-161.
[25] J. Lin, C. Yang and H. Wu, “A 2.5-Gb/s DLL-based burst-mode clock and data recovery circuit with 4 × oversampling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, pp. 791-795, April 2015
[26] W. Bae, G. Jeong, K. Park, S. Cho, Y. Kim and D. Jeong, “A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s forwarded-clock receiver with a stuck-free delay-locked loop and a half-bit delay line in 65-nm CMOS technology,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 9, pp. 1393-1403, Sept. 2016.
[27] Y. -S. Lin, M. -S. Li and C. -Y. Yang, “A 2.7-Gb/s clock and data recovery circuit based on D/PLL,” IEEE International System-on-Chip Conference, Sept. 2019, pp. 284-288.
[28] X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS data recovery DLL using half-frequency clock,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp.711–715, Jun.2002.
[29] J. Terada, K. Nishimura, S. Kimura, H. Katsurai, N. Yoshimoto and Y. Ohtomo, “A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2921-2928, Dec. 2008.
[30] K. Kishine et al., “A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, no. 5, pp. 1288-1295, May 2015.
[31] J. Kim, and D.-K. Jeong, “Multi-gigabit-rate clock and data recovery based on blindoversampling,” IEEE Commun. Mag., vol. 41, pp. 68–74, Dec. 2003.
[32] G. Wu et al., “A 1–16 Gb/s all-digital clock and data recovery with a wideband highlinearity phase interpolator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 7, pp. 2511-2520, July 2016.
[33] Y. Xia et al., "A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR," IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 12, pp. 5432-5442, Dec. 2020
[34] S. -C. Chang and S. -I. Liu, "A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 1, pp. 161-165, Jan. 2021
[35] S. Hu, C. Jia, K. Huang, C. Zhang, X. Zheng and Z. Wang, "A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS," 2012 IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea (South), 2012, pp. 309-312
[36] Xueyi Yu, Jian Qiao, Woogeun Rhee, Joon-Young Park, Kyongsu Lee and Zhihua Wang, "A semi-digital cascaded CDR with fast phase acquisition and adaptive resolution control," Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, Hsin Chu, 2010, pp. 307-310
[37] B. Liu, Z. Wang, T. Zhang, L. Zhang, S. Yang and L. Yang, "A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard," 2021 6th International Conference on Integrated Circuits and Microsystems (ICICM), Nanjing, China, 2021, pp. 5-13
[38] S. Sen, U. Upadhyaya, K. R. Kondreddy, A. Goyal, S. Goyal and S. Gupta, "A Low Jitter Digital Loop CDR Based 8–16 Gbps SerDes in 65 nm CMOS Technology," 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), Guwahati, India, 2021, pp. 216-221
[39] H. -J. Jeon, R. Kulkarni, Y. -C. Lo, J. Kim and J. Silva-Martinez, "A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy," IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1398-1415, June 2013
[40] Y. Miki, T. Saito, and H. Yamashita, et al. “A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking,” IEEE J. of Solid-State Circuits, vol. 39, no. 4, pp. 613-621, Apr. 2004.
[41] 陳炳宏 , “應用於 SATA-III之 6 Gbps半速率時脈與資料回復電路 ,” 碩士論文 , 國立
中央大學 , 2009.
[42] 鄭柏旻 , “具電容放大技術和自適應迴路增益控制器之 5 Gbps雙路徑時脈與資料
回復電路 ,”碩士論文 , 國立中央大學 , 2017.
[43] S. Sidiropoulos and M. A. Horowitz, “A semidigital dual delay-locked loop,” IEEE J. of Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.
[44] 鄭宇亨 , “具資料獨立相位追蹤補償技術之 10 Gbps 半速率時脈與資料回復電路
,”碩士論文 , 國立中央大學 , 2018.
[45] S. Lee, R. Harjani and T. Oh, "Pseudo-Reference Counter-Based FLL for 6 Gb/sReference-Less CDR in 65-nm CMOS," IEEE Transactions on Circuits andSystems II: Express Briefs, vol. 69, no. 4, pp. 2096-2100, April 2022.
[46] W. Kim, W. Hong, J. J. Kim and M. Lee, "A 5.4-Gb/s, 0.57-pJ/bit, Single-LoopReferenceless CDR With an Unlimited Bilateral Frequency Detection Scheme," IEEE Transactions n Very Large Scale Integration (VLSI) Systems, vol. 31, no. 6,pp. 851-860, June 2023.
[47] W. Xiao, Q. Huang, H. Mosalam, C. Zhan, Z. Li and Q. Pan, "A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 2, pp. 634-644, Feb. 2022
[48] C. Yu, E. Sa, S. Jin, H. Park, J. Shin and J. Burm, "A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 55, no. 10, pp. 2831-2841, Oct. 2020
[49] H. Seo et al., "A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 2, pp. 411-415, Feb. 2023

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2024-1-22

推文