基於輕量級語義分割網路結合自動生成像素級標籤技術的晶圓圖混合型缺陷模式識別

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姓名

洪庭幃(Ting-Wei Hong) 查詢紙本館藏

畢業系所

工業管理研究所

論文名稱

基於輕量級語義分割網路結合自動生成像素級標籤技術的晶圓圖混合型缺陷模式識別
(Wafer Map Mixed-Type Defect Pattern Recognition based on Lightweight Semantic Segmentation Network with Automatic Pixel-Level Label Generation Technique)

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摘要(中)

晶圓製程包含數百個複雜步驟，完成後需進行晶片測試。識別晶圓圖中的缺陷模式有助於找出缺陷原因並優化製程，例如CMP可能導致中心、刮痕、邊緣等缺陷。迅速準確地辨識缺陷模式對提高產量至關重要。而近期在晶圓圖缺陷模式識別領域應用深度學習的研究大大加速了缺陷檢測的過程。然而當不同的缺陷混合在同一塊晶圓上時，混合型晶圓缺陷相較單類別晶圓缺陷複雜，對於晶圓缺陷模式的識別非常困難，而使用語意分割可以有效的辨識混合晶圓缺陷，但語意分割的訓練資料要求像素級晶圓圖標籤。故在本文中，我們提出了一個自動晶圓圖標籤生成技術，並通過使用語義分割方法在晶圓圖上分割不同的缺陷模式。

摘要(英)

The wafer fabrication process involves hundreds of complex steps, followed by chip testing upon completion. Identifying defect patterns in wafer maps helps identify the causes of defects and optimize the process. For example, Chemical Mechanical Polishing (CMP) may lead to defects such as center defects, scratches, and edge defects due to particle aggregation or pad hardening during the CMP process. Rapid and accurate identification of defect patterns is crucial for improving yield. Recent research applying deep learning to defect pattern recognition in wafer maps has significantly accelerated the defect detection process. However, when different defects are mixed on the same wafer, mixed-type wafer defects are more complex compared to single-type defects, making defect pattern recognition challenging. Semantic segmentation can effectively identify mixed wafer defects, but training data for semantic segmentation requires pixel-level wafer map labels. Therefore, in this study, we propose an automatic wafer map labeling technique and segment different defect patterns on wafer maps using semantic segmentation.

關鍵字(中)

★ 晶圓缺陷辨識
★ 語意分割
★ 資料生成

關鍵字(英)

★ wafer defect recognition
★ semantic segmentation
★ data generation

論文目次

摘要 i
Abstract ii
目錄 iii
圖目錄 iv
第一章緒論 1
1.1 研究背景與動機 1
1.2 問題定義 3
1.3研究目的 3
1.4研究方法 3
第二章文獻回顧 4
2.1單一類別缺陷模型辨識 4
2.2 混合類別缺陷模型辨識 5
2.3 語意分割 7
第三章方法論 10
3.1 自動生成像素級標籤技術 11
3.1.1 生成單類別晶圓缺陷圖 11
3.2 輕量級語意分割網路 18
3.2.1編碼器 18
3.2.2 Efficient Transformer 20
3.2.2 解碼器 21
第四章實驗結果 23
4.1數據及資料前處理 23
4.2實驗設置 24
4.3分類結果 25
第五章結論 28
參考文獻 30

參考文獻

[1] Batool, U., M. I. Shapiai, H. Fauzi, & J. X. Fong. "Convolutional neural network for imbalanced data classification of silicon wafer defects." 2020 16th IEEE International Colloquium on Signal Processing & Its Applications (CSPA). IEEE, 2020, 230-235.
[2] Bochkovskiy, A., C. Y. Wang, & H. Y. M. Liao. "Yolov4: Optimal speed and accuracy of object detection." arXiv preprint arXiv:2004.10934, 2020.
[3] Byun, Y., & J. G. Baek. "Mixed Pattern Recognition Methodology on Wafer Maps with Pre-trained Convolutional Neural Networks." ICAART (2), 2020, 974-979.
[4] Carion, N., F. Massa, G. Synnaeve, N. Usunier, A. Kirillov, & S. Zagoruyko. "End-to-end object detection with transformers." European Conference on Computer Vision. Cham: Springer International Publishing, 2020, 213-229.
[5] Chiu, M. C., & T. M. Chen. "Applying data augmentation and mask R-CNN-based instance segmentation method for mixed-type wafer maps defect patterns classification." IEEE Transactions on Semiconductor Manufacturing 34.4, 2021, 455-463.
[6] He, K., X. Zhang, S. Ren, & J. Sun. "Deep residual learning for image recognition." Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2016, 770-778.
[7] He, K., G. Gkioxari, P. Dollár, R. Girshick. "Mask r-cnn." Proceedings of the IEEE International Conference on Computer Vision, 2017, 2961-2969.
[8] Huang, G., Z. Liu, L. Van Der Maaten, & K. Q. Weinberger. "Densely connected convolutional networks." Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 2017, 4700-4708.
[9] Jin, C. H., H. J. Na, M. Piao, G. Pok, & K. H. Ryu. "A novel DBSCAN-based defect pattern detection and classification framework for wafer bin map." IEEE Transactions on Semiconductor Manufacturing 32.3, 2019, 286-292.
[10] Kahng, H., & S. B. Kim. "Self-supervised representation learning for wafer bin map defect pattern classification." IEEE Transactions on Semiconductor Manufacturing 34.1, 2020, 74-86.
[11] Kyeong, K., & H. Kim. "Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks." IEEE Transactions on Semiconductor Manufacturing 31.3 ,2018, 395-402.
[12] Kong, Y., & D. Ni. "Recognition and location of mixed-type patterns in wafer bin maps." 2019 IEEE International Conference on Smart Manufacturing, Industrial & Logistics Engineering (SMILE). IEEE, 2019, 4-8.
[13] Kong, Y., & D. Ni. "Qualitative and quantitative analysis of multi-pattern wafer bin maps." IEEE Transactions on Semiconductor Manufacturing 33.4 ,2020, 578-586.
[14] Nakazawa, T., & D. V. Kulkarni. "Wafer map defect pattern classification and image retrieval using convolutional neural network." IEEE Transactions on Semiconductor Manufacturing 31.2, 2018, 309-314.
[15] Nag, S., D. Makwana, S. Mittal, C. K. Mohan. "WaferSegClassNet-A light-weight network for classification and segmentation of semiconductor wafer defects." Computers in Industry 142, 2022, 103720.
[16] Piao, M., C. H. Jin, J. Y. Lee, & J. Y. Byun. "Decision tree ensemble-based wafer map failure pattern recognition based on radon transform-based features." IEEE Transactions on Semiconductor Manufacturing 31.2, 2018, 250-257.
[17] Redmon, J., & A. Farhadi. "Yolov3: An incremental improvement." arXiv preprint arXiv:1804.02767, 2018.
[18] Shinde, P. P., P. P. Pai, & S. P. Adiga. "Wafer defect localization and classification using deep learning techniques." IEEE Access 10, 2022, 39969-39974.
[19] Song, D., B. Liu, & Y. Li. "Based on end-to-end object detection algorithm with transformers for detecting wafer maps." 2022 International Conference on Computer Network, Electronic and Automation (ICCNEA). IEEE, 2022, 297-302.
[20] Wang, J., C. Xu, Z. Yang, J. Zhang, X. Li. "Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition." IEEE Transactions on Semiconductor Manufacturing 33.4, 2020, 587-596.
[21] Wang, R., & N. Chen. "Wafer map defect pattern recognition using rotation-invariant features." IEEE Transactions on Semiconductor Manufacturing 32.4, 2019, 596-604.
[22] Wei, Y., & H. Wang. "Mixed-type wafer defect recognition with multi-scale information fusion transformer." IEEE Transactions on Semiconductor Manufacturing 35.2, 2022, 341-352.
[23] Xu, G., J. Li, G. Gao, H. Lu, J. Yang, & D. Yue. "Lightweight real-time semantic segmentation network with efficient transformer and CNN." IEEE Transactions on Intelligent Transportation Systems 24.12, 2023, 15897-15906.
[24] Yan, J., Y. Sheng, & M. Piao. "Semantic Segmentation-Based Wafer Map Mixed-Type Defect Pattern Recognition." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42.11 , 2023, 4065-4074.

指導教授

葉英傑(Ying-Chieh Yeh)

審核日期

2024-7-23

推文