三維半導體元件模擬器之開發及SOI MOSFET特性分析

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姓名

黃朝新(Chau-Hsin Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

三維半導體元件模擬器之開發及SOI MOSFET特性分析
(Development of 3-D semiconductor device simulator and analysis of SOI MOSFET)

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摘要(中)

本論文主要以階層化不完全LU法(L-ILU method)的稀疏矩陣解法器配合分離法(decoupled method)而建立一套三度空間的半導體元件模擬器。為了印證所開發元件模擬器的正確性，我們將使用Medici和Davinci軟體來印證。而在元件應用上，我們使用三度空間的元件模擬器來模擬真實的SOI元件，並使用body-tied的等效方式來使SOI元件能更穩定的操作。並且，我們也利用SOI DTMOS和在SOI元件上使用不同的閘極結構來使SOI元件能達到低功率和高效率的特性。其間，為了節省記憶體空間，我們也開發了一套能近似三度空間特性的二維等效模擬軟體。

摘要(英)

In this thesis, we use the Levelized Incomplete LU method and decoupled method to build up a three-dimensional device simulator. Moreover, we use the Medici and Davinci software to prove the validity of our 3-D device simulator. In 3-D device application, we use the three-dimensional device simulator to simulate the real silicon-on-insulator (SOI) device. Moreover, we use the body-tied method to obtain more stable device operation. Furthermore, we use the methods of SOI DTMOS and different gate structures to obtain the characteristics of lower power and high efficiency. In the meantime, we developed a quasi-3D device simulator to represent 3-D characteristics by using a 2-D device simulator for memory reduction.

關鍵字(中)

★ 三維半導體
★ 元件模擬

關鍵字(英)

★ SOI MOSFET
★ 3D decoupled method
★ connection-table
★ three-dimensional device simulator

論文目次

Contents
1. Introduction 1
2. Levelized Incomplete LU Method and Connection-Table
Construction 3
2.1 Introduction to Levelized Incomplete LU Methods ……………...3
2.2 Connection-Table Construction for A Simple Circuit Network ….5
2.3 Connection-Table Construction for 2-D Device Simulation …...8
2.4 Connection-Table Construction for 3-D Device Simulation ……12
3. Decoupled and Coupled Methods in Three-Dimensional
Simulation 16
3.1 Three-Dimensional Decoupled Method……………….……….16
3.2 Comparison between 3-D Decoupled and Coupled Methods……17
3.3 Equivalent Circuit Model for 3-D Decoupled Method ………….20
3.4 3-D Device Characteristic and Application ……………………..26
3.4.1 3-D p-n Diode Simulation ………………..……………….26
3.4.2 The 3-D MOSFET Simulation ………………………….28
3.5 Comparison of Our Device Simulator, Medici and Davinci …....30
3.5.1 Comparison of p-n Diode ………………………...……….30
3.5.2 Comparison of MOSFET …………………………………32
3.5.3 Comparison of SOI MOSFET……………………………33
4. 3-D Silicon-On-Insulator MOSFET Simulation 35
4.1 SOI MOSFET …………….…………………………………………….35
4.1.1 SOI MOSFET Structure …………….…….……………….36
4.1.2 Partially and Fully Depleted SOI Devices ………...…….37
4.2 Substrate Bias Effect in Body-Tied SOI MOSFET ….……………41
4.3 SOI Dynamic Threshold Voltage MOSFET ……….……………44
4.4 Quasi-3D SOI MOSFET Simulation ……………………………45
4.5 The SOI DTMOS with Different Gate Structures …………….48
5. Conclusion 51

參考文獻

Reference
[1] Y.-T. Tsai, C.-Y. Lee and ,.M-K. Tsai, “Levelized incomplete LU method and its application to semiconductor device simulation,” Solid-State Electronics, vol. 44, pp. 1069-1075, 2000.
[2] H. K. Gummel, “A self-consistent iterative scheme for one-dimensional steady state transistor calculations,” IEEE Trans. Electron Devices, vol. ED-11, pp. 455-465, 1964.
[3] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer, 1984.
[4] C.-C. Chang, C.-H. Huang, J.-F. Dai, S.-J. Li, and Y.-T. Tsai, “3-D numerical device simulation including equivalent-circuit model,” in IEDMS 2002, p. 542-544.
[5] S. Maeda, Y. Hirano, Y. Yamaguchi, T. Iwamatsu, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, H. Abe, and T. Nishimura, “Substrate-bias effect and source–drain breakdown characteristics in body-tied short-channel SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 1, p. 151, January 1999.
[6] W.-C. Lo, S.-J. Chang, C.-Y. Chang, Fellow, IEEE, and T.-S. Chao, “Impacts of gate structure on dynamic threshold SOI nMOSFETs,” IEEE Electron Device Lett., vol. 23, no. 8, p. 497, August 2002.
[7] K. Mayaram and D. O. Pederson, “Coupling algorithms for mixed-level circuit and device simulation,” IEEE Transactions on computer-aided design, vol. 11, no. 8, pp. 1003-1010, 1992.
[8] C.-L. Teng, “An equivalent circuit approach to mixed-level device and circuit simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[9] C. Y. Chang and S. M. Sze, ULSI devices, Chapter 5, John Wiley & Sons Inc., 2000.
[10] S. M. Sze, Modern Semiconductor Device Physics, Chapter 3, John Wiley & Sons Inc., 1998.
[11] W. Chen, Y. Taur, D. Sadana, K. A. Jenkins, J. Sun, and S. Cohen, “Suppression of the SOI floating-body effects by linked-body device structure,” in Symp. VLSI Technol., p. 92, 1996.
[12] D. Suh and J. G. Fossum, “Dynamic floating-body instabilities in partially depleted SOI CMOS circuits,” in IEDM Tech. Dig., p. 661, 1994.
[13] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” in IEDM Tech. Dig., p. 809, 1994.
[14] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur, “Channel profile optimization and device design for low-power highperformance dynamic-threshold MOSFET,” in IEDM Tech. Dig., p. 113, 1996.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2003-6-20

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