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姓名 魏健宇(Chien-Yu Wei) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 使用100-nm GaAs pHEMT 製程之 Q 頻段低雜訊放大器
(Q-band Low-Noise Ampli ers in 100-nm GaAs pHEMT Technology)相關論文 檔案 [Endnote RIS 格式]
[相關文章]
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至系統瀏覽論文 (2027-8-7以後開放)
摘要(中) 本論文為使用WIN100-nm GaAs pHEMT 製程，設計應用於第
五代行動通訊中毫米波頻段之低雜訊放大器。第二章設計48-GHz
band 架構為共源極單極低雜訊放大器。第三章設計48-GHz band 兩
顆單級疊接低雜訊放大器，架構分別為輸入、輸出皆以傳輸線並聯方
式匹配與輸入、輸出皆以電容並聯傳輸線匹配方式設計。
第二章中，我們設計一個應用於48-GHz band 低雜訊放大器架
構為commom source，匹配設計之傳輸線並聯方式，輸入端與輸出端
搭配in band bypass and out of band bypass 使電路更加穩定。尺寸為
2×25 µm 小訊號量測結果增益大於6.7 dB、輸入端的反射損耗大於
4.6 dB、輸出端的反射損耗大於28dB，雜訊指數在48GHz時為1.96
dB，而線性度IP1dB 為 −2.5 dBm。在設計之頻率量測與模擬結果整
體趨勢一致。
第三章中，我們設計一個應用於48-GHz band 之疊接低雜訊放
大器，匹配方式設計有兩種，第一種為傳輸線並聯方式，第二種為電
容並聯傳輸線方式，兩電路皆在輸入端與輸出端搭配inbandbypass
and out of band bypass 使電路更加穩定。電路圖 3.1 使用傳輸線並聯
匹配，小訊號量測結果增益大於12.9dB、雜訊指數在48GHz 時為
2.67 dB，增益整體往低頻頻偏。重新偵錯模擬後使電路在設計之中心
頻率，增益以及輸入與輸出的返回損耗趨勢一致相同。重新偵錯模擬
後的增益為12.7 dB 與量測時 12.9 dB 較為接近，而在 44 GHz 線性
度IP1dB 為 −10 dBm。電路圖 3.2 使用電容並聯傳輸線方式匹配,小
訊號量測結果增益為12.5dB、雜訊指數在48GHz時為2.68 dB，增
益整體往低頻頻偏。重新偵錯模擬後使電路在設計之中心頻率，增益
I
趨勢一致相同。重新偵錯模擬後的增益為12.3dB與量測時12.5 dB
較為接近，而在44GHz線性度IP1dB 為−18dBm。摘要(英) This paper utilizes the WIN 100-nm GaAs pHEMT process to
design low-noise ampli ers intended for the millimeter-wave frequency
bands in fth-generation mobile communication. Chapter 2 presents
the design of a common-source single-stage LNA structure for the 48
GHz band frequency range. Chapter 3 focuses on the design of two
cascaded single-stage LNAs for the 48-band frequency range. These de
signs involve input and output matching using transmission line parallel
matching in one case and capacitor parallel transmission line matching
in the other.
In Chapter 2, we designed an LNA for the 48-GHz band. The
matching network employs transmission line shunt elements, with in
band and out-of-band bypasses at the input and output to enhance
circuit stability.For a device size of 2×25 µm, the small-signal measure
ment results show a gain greater than 6.7 dB, input return loss greater
than 4.6 dB, output return loss greater than 28 dB, NF of 1.96 dB at
48 GHz, and 1 dB compression point of −2.5 dBm. The measured and
simulated frequency performance align well.
In Chapter 3, we designed a cascaded low-noise ampli er for the 48
GHz band with two matching methods: the rst employs transmission
line parallel matching, and the second uses capacitor-parallel transmis
sion line matching. Both circuits utilize in-band bypass and out-of-band
bypass at the input and output to enhance circuit stability. Circuit di
agram 3.1 utilizes transmission line parallel matching. The small-signal
III
measurement results show a gain greater than 12.9 dB and a noise gure
of 2.67 dB at 48 GHz, with the gain tending towards lower frequencies.
After debugging simulation, the circuit maintains consistent trends in
gain, input, and output return loss at the design center frequency. The
revised gain after debugging simulation is 12.7 dB, closely matching the
measured 12.9 dB, with a 1 dB compression point of −10 dBm at 44
GHz.
Circuit diagram 3.2 employs capacitor-parallel transmission line
matching. The small-signal measurement results show a gain greater
than 12.5 dB and a noise gure of 2.68 dB at 48 GHz, with the gain sim
ilarly trending towards lower frequencies. After debugging simulation,
the circuit maintains consistent trends in gain at the design center fre
quency. The revised gain after debugging simulation is 12.3 dB, closely
matching the measured 12.5 dB, with a 1 dB compression point of −18
dBm at 44 GHz關鍵字(中) ★ Q 頻段低雜訊放大器 關鍵字(英) 論文目次 摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX
第一章緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1研究動機與背景. . . . . . . . . . . . . . . . . . . . 1
1.2論文架構. . . . . . . . . . . . . . . . . . . . . . . . 2
第二章48-GHzband共源極低雜訊放大器. . . . . . . . . . . 3
2.1簡介. . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2設計考量. . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1傳輸線並聯匹配方式. . . . . . . . . . . . . . . . . . 5
2.2.2挑選Bypass尺寸技巧. . . . . . . . . . . . . . . . . 5
2.2.3輸入端與輸出端皆接上DCBlock. . . . . . . . . . . 5
2.2.4模擬結果. . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.5量測結果. . . . . . . . . . . . . . . . . . . . . . . . 11
2.3結果與討論. . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1單級共源極低雜訊放大器. . . . . . . . . . . . . . . 14
第三章48-GHzband疊接低雜訊放大器. . . . . . . . . . . . 17
3.1簡介. . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2電路模擬與量測. . . . . . . . . . . . . . . . . . . . 20
3.2.1電路設計. . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2匹配方式. . . . . . . . . . . . . . . . . . . . . . . . 21
3.3模擬結果. . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1使用傳輸線並聯設計模擬結果及匹配網路架構圖. . 23
3.3.2使用電容並聯傳輸線設計架構模擬結果. . . . . . . 27
3.4量測結果. . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.1使用傳輸線並聯設計架構量測結果. . . . . . . . . . 31
3.4.2使用電容並聯傳輸線設計架構量測結果. . . . . . . 34
3.5重新偵錯模擬結果. . . . . . . . . . . . . . . . . . . 37
3.5.1使用傳輸線並聯設計架構之電路偵錯. . . . . . . . . 37
3.5.2使用電容並聯傳輸線設計架構之電路偵錯. . . . . . 39
V
3.6結果與討論. . . . . . . . . . . . . . . . . . . . . . . 42
3.6.1使用傳輸線並聯設計架構. . . . . . . . . . . . . . . 42
3.6.2使用電容並聯傳輸線設計架構. . . . . . . . . . . . 42
第四章結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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