適用於合成孔徑雷達之即時都普勒參數估測硬體設計與實作

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姓名

陳柏達(Po-Ta Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於合成孔徑雷達之即時都普勒參數估測硬體設計與實作
(Real-Time Hardware Design and Implementation of Doppler Parameter Estimation for Synthetic Aperture Radar)

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至系統瀏覽論文 (2029-7-31以後開放)

摘要(中)

合成孔徑雷達透過裝載在衛星或是飛機上，能夠不受天氣、日夜影響的遙測地表，生成二維的影像。在載體飛行的過程中，雷達與目標物的距離變化會產生都普勒效應，精確的都普勒參數對於測距都普勒演算法的跨耦合補償相當重要。基於相位演算法和多視互乘頻率演算法能分別應用於基頻都普勒質心估測與都普勒歧異值估測。而估測前的區塊切割，能透過品質篩選刪除雜訊大的區塊，只選擇可靠的估測結果。我們提出相位離散度作為品質篩選，多視互乘頻率演算法的估測成功率能從69%提升至75%。在硬體設計上，將都普勒參數和測距都普勒演算法做整合設計，提出了共用測距壓縮資料的流程圖，並針對於硬體運算做簡化，同時考量運算延遲、產出率與量化後之效能。為了減少硬體用量，在三次測距壓縮的硬體實作上，使用運算排程和共用技巧，與二次測距壓縮的部分硬體共用，在少量硬體的增加下，最終成像能達到36dB的量化訊雜比。對於都普勒參數估測的硬體實作，透過排程減少複數乘法器、累加器和位元反轉記憶體，比原本設計共減少28%的乘法器和25%的記憶體。而在文獻比較上，我們的設計有快於4倍的處理速度。為了支援1.6秒內的即時運算，設計滿足51Gbps存取速度的測距都普勒演算法高頻寬記憶體介面，處理速度比近期文獻快至少2.93倍；同時設計記憶體空間配置，控制PCIe介面在電腦與FPGA間高速傳輸。另一方面在電腦端的處理流程，透過混合式編譯加速資料格式轉換，完成影像的傳輸與處理。最後，我們將所有操作整合於使用者圖形化介面，完成方便於使用者操作的成像加速處理器。

摘要(英)

Synthetic Aperture Radar (SAR) as a payload on satellites or aircraft can remotely sense the Earth’s surface regardless of weather conditions. During sensing, the movement between the radar and the target results in the Doppler effect. Accurate Doppler parameters are crucial for cross-coupling compensation in the range Doppler algorithm (RDA). The phase-based algorithm and the Multilook Beat Frequency Algorithm (MLBF) can be applied to baseband Doppler centroid estimation and Doppler ambiguity estimation, respectively. Prior to estimation, block partition can eliminate noisy blocks through quality measurement. We propose phase spread as a quality measurement index, which can improve the success rate of estimation in MLBF from 69% to 75%. We then integrate the function of Doppler parameter estimation into the RDA processor. The range compressed data from RDA are shared to simplify hardware computation. The computation latency as well as throughput and performance of quantization are all investigated. To reduce hardware utilization in the implementation of third-order secondary range compression to support larger-squint angles, scheduling and sharing techniques are employed. For hardware implementation of Doppler parameter estimation, we totally save 28% multipliers and 25% memory, and the processing speed is four times faster than the prior work and thus can deal with real-time processing for a SAR image of size 32K×8K. In order to support real-time operations for SAR imaging within 1.6 seconds, an RDA interface to high bandwidth memory (HBM) is realized with a 51Gbps throughput. Finally, we design the graphical user interface which can benefit users to operate the imaging acceleration processor easily and provide configurability.

關鍵字(中)

★ 合成孔徑雷達
★ 都普勒質心估測
★ 即時影像處理
★ 三次測距壓縮硬體實作
★ 都普勒參數估測硬體實作
★ 高頻寬記憶體介面設計
★ 測距都普勒演算法處理器整合

關鍵字(英)

★ Synthetic aperture radar
★ Doppler centroid estimation
★ Real-time processing
★ Hardware implementation of third-order secondary range compression
★ Hardware implementation of Doppler parameter estimation
★ Hardware design of interface of high bandwidth memory
★ Integration in processor of range Doppler algorithm

論文目次

摘要 i
Abstract ii
目錄 iii
表目錄 vi
圖目錄 viii
第一章緒論 1
1.1 研究動機 1
1.2 研究方法 1
1.3 論文組織 2
第二章合成孔徑雷達成像演算法 3
2.1 合成孔徑雷達成像系統 3
2.2 測距都普勒演算法(Range Doppler Algorithm, RDA)[1] 5
第三章都普勒參數估測演算法 14
3.1 都普勒質心 14
3.2 基頻都普勒質心估測(Baseband Doppler Centroid Estimation) 17
3.2.1 基於量值的方法[2] 17
3.2.2 基於相位的方法[2] 20
3.2.3 基頻都普勒質心估測演算法比較 23
3.3 都普勒歧異值估測(Doppler Ambiguity Estimation) 25
3.3.1 多視互相關演算法(Multilook Cross Correlation Algorithm, MLCC)[2] 25
3.3.2 多視互乘頻率演算法(Multilook Beat Frequency Algorithm, MLBF)[2] 29
3.3.3 都普勒歧異值估測演算法比較 31
3.4 區塊品質評估與篩選(Quality Measurement) 32
3.4.1 相位離散度(Phase Spread) 32
3.4.2 加權相位離散度(Weighted Phase Spread) 35
3.4.3 品質評估與篩選方法比較 36
3.4.4 品質篩選與都普勒質心重建 38
第四章都普勒參數估測演算法硬體評估 39
4.1 都普勒參數估測硬體流程評估 39
4.2 都普勒參數估測硬體運算評估 43
4.2.1 視窗萃取流程檢驗 43
4.2.2 測距方向資料簡化 45
4.2.3 相位離散度運算共用與近似 47
4.3 都普勒參數估測硬體延遲評估 49
4.4 都普勒參數估測硬體位元數量化評估 52
4.5 都普勒參數估測硬體資源用量評估 61
第五章三次測距方向壓縮與都普勒參數估測硬體架構設計與整合 62
5.1 測距都普勒演算法(RDA)硬體實現[1] 62
5.2 三次測距方向壓縮(TRC)硬體設計與整合 63
5.3 都普勒參數估測硬體設計 69
5.3.1 平坦窗濾波器硬體實現 70
5.3.2 可變長度測距傅立葉反轉換硬體實現 72
5.3.3 都普勒質心估測與品質篩選硬體實現 75
5.3.4 都普勒參數估測硬體整合 78
5.3.5 遷移函數硬體實現 80
第六章高頻寬記憶體介面評估 83
6.1 現場可程式化邏輯閘陣列(FPGA)端傳輸介面設計 83
6.1.1 高頻寬記憶體(High Bandwidth Memory, HBM) 84
6.1.2 高階可擴充介面(Advanced eXtensible Interface, AXI) 85
6.1.3 區塊記憶體(Block Random-Access Memory, BRAM) 88
6.1.4 測距都普勒介面(RDA Interface)評估與設計 89
6.1.5 傳輸速度實驗與驗證 93
6.1.6 符合四種傅立葉轉換的記憶體定址索引設計 97
6.2 電腦(PC)端傳輸介面設計 99
6.2.1 PC端與FPGA端傳輸資料方式評估 99
6.2.2 傳輸流程控制與HBM空間配置 101
6.2.3 PC端資料前處理與後處理 104
6.2.4 使用者圖形化介面(Graphical User Interface, GUI) 110
第七章結論 113
參考文獻 115

參考文獻

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指導教授

蔡佩芸(Pei-Yun Tsai)

審核日期

2024-8-15

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