基於動態隨機存取記憶體之近端與內存運算記憶體測試

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姓名

張晉維(Jin-Wei Zhang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於動態隨機存取記憶體之近端與內存運算記憶體測試
(Testing of DRAMs for Near and In-Memory Computing)

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至系統瀏覽論文 (2029-8-21以後開放)

摘要(中)

現代馮·諾依曼計算架構在處理數據密集型運算時，數據移動成為性能和功率消耗的瓶頸。內存運算（Computing-in-Memory, CIM）或近端運算（Computing-near-Memory, CNM）被視為具有發展潛力的方法，其中包括在內存陣列或週邊電路中進行運算，或使用3D堆疊架構將內存堆疊於邏輯芯片之上。然而，這些方法增加了架構的複雜性，因此有必要發展有效的測試與修復方法。在本論文中，我們首先對基於DRAM的CIM進行了故障分析，並提出了一種行軍式測試（March Test），以涵蓋內存模式與運算模式下所定義的故障。針對包含N個字元的DRAM CIM，該行軍式測試需要執行12N次寫入操作、5N次讀取操作及6N次運算操作。其次，我們探討了3D DRAM的I/O介面測試與修復。針對具有可重構I/O介面的3D DRAM，我們採用了環回測試方法來檢測可重構I/O介面的參數故障，並提出了一種良好配置識別演算法，用於識別可重構I/O介面的最佳配置。與窮舉搜尋法相比，我們的方法在不犧牲修復率的情況下，對於具有16個通道且每個通道具有128位I/O的4層堆疊3D DRAM，能夠減少22%的測試時間。對於相同I/O條件下的8層堆疊，我們的方法能夠減少26%的測試時間，修復率僅降低0.67%。此外，我們設計了一個基於台積電90nm製程的內建自我修復（Built-In Self-Repair, BISR）電路，用於檢測與修復參數故障。當內存大小為512Mb時，BISR電路的面積開銷僅為0.34%。

摘要(英)

Data movement of modern von Neumann computing architecture for data-intensive computation is the bottleneck of performance and energy. Computing-in-memory (CIM) or computing-near-memory (CNM) has been considered as a promising approach, involving computations within memory arrays or peripherals, or using 3D stacking architectures to stack memory on top of logic chips. However, these approaches increase the complexity of the architecture, necessitating the development of effective test and repair methods. In this thesis, we first execute the fault analysis for a DRAM-based CIM and then a March test is proposed to cover the defined faults in both memory mode and computing mode. The March test requires 12N Write operations, 5N Read operations, and 6N Computing operations for a DRAM-based CIM with N words. Secondly, the testing and repair of the I/O interface of 3D DRAMs is introduced. Consider a 3D DRAM with a reconfigurable I/O interface and a loopback test method is used to detect parametric faults of the reconfigurable I/O interface. We propose a good configuration identification algorithm to identify a good configuration of the reconfigurable I/O interface. In comparison with an exhaustive search approach, our approach can reduce 22% of test time without sacrificing the repair rate for a 4-die stacked 3D DRAM with 16 channels, each of which has 128-bit I/Os. For an 8-die stack in the same I/O condition, our approach can reduce test time by 26% at a 0.67% decrease in the repair rate. Additionally, we design a built-in self-repair (BISR) circuit for detecting and repairing parametric faults using the TSMC 90nm standard cell library. The area overhead of the BISR circuit is only 0.34% while the memory size is 512Mb.

關鍵字(中)

★ 記憶體內運算
★ 記憶體測試
★ 三維隨機存取記憶體
★ 內建自我修復

關鍵字(英)

★ Computing-In-Memories
★ Memory Testing
★ 3D DRAM
★ BISR

論文目次

Introduction 1
1.1 Dynamic Random AccessMemory 1
1.2 DRAM-based Computing-In-Memory 2
1.3 Test and Repair of 3D-Stacked DRAMs 4
1.3.1 Loopback Test 5
1.3.2 Reconfigurable I/O Interface 5
1.4 Motivation 6
1.5 Contribution 8
1.6 Thesis Organization 8
2 FaultModeling and Testing for DRAM-based CIMs 9
2.1 DRAM-based CIMs 9
2.1.1 Triple-Row Activation (TRA) 9
2.1.2 Fast Row Copy Using RowClone 10
2.2 Electrical Defect and SimulationModel 11
2.2.1 Electrical Defect 12
2.2.2 SimulationModel 13
2.3 FaultModeling Flow 19
2.4 Test Development 19
2.4.1 FaultModels inMemoryMode 19
2.4.2 FaultModels in ComputingMode 22
2.4.3 Fault Analysis 23
2.4.4 Test Algorithm 25
2.5 Summary 34
3 Good Configuration IdentificationMethod for 3D DRAMs with Reconfigurable I/O Interface 35
3.1 Reconfigurable I/O Interface for Tolerating Delay Faults 35
3.2 Test Architecture 40
3.3 Proposed Good Configuration Identification Algorithm 41
3.4 Simulation Result 48
3.4.1 Repair Rate Analysis 48
3.4.2 Reduction Test Runs Analysis 53
3.5 Hardware Implementation 56
4 Conclusion and FutureWork 62

參考文獻

[1] J.-S. Kim, C. S. Oh, H. Lee, D. Lee, H. R. Hwang, S. Hwang, B. Na, J. Moon, J.-G. Kim, H. Park, J.-W. Ryu, K. Park, S. K. Kang, S.-Y. Kim, H. Kim, J.-M. Bang, H. Cho, M. Jang, C. Han, J.-B. Lee, J. S. Choi, and Y.-H. Jun, “A 1.2 V 12.8 Gb/s 2 GB mobile wide-I/O DRAM with 4 × 128 I/Os using TSV based stacking,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 107–116, 2012.
[2] U. Kang, H.-J. Chung, S. Heo, S.-H. Ahn, H. Lee, S.-H. Cha, J. Ahn, D. Kwon, J. H. Kim, J.-W. Lee, H.-S. Joo, W.-S. Kim, H.-K. Kim, E.-M. Lee, S.-R. Kim, K.-H. Ma, D.-H. Jang, N.-S. Kim, M.-S. Choi, S.-J. Oh, J.-B. Lee, T.-K. Jung, J.-H. Yoo, and C. Kim, “8GB 3D DDR3 DRAM using through-silicon-via technology,” in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, pp. 130–131, 131a.
[3] D. U. Lee, K. W. Kim, K. W. Kim, K. S. Lee, S. J. Byeon, J. H. Kim, J. H. Cho, J. Lee, and J. H. Chun, “A 1.2 V 8 GB 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective I/O test circuits,” IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 191–203, 2015.
[4] J. S. Kim, D. Senol Cali, H. Xin, D. Lee, S. Ghose, M. Alser, H. Hassan, O. Ergin, C. Alkan, and O. Mutlu, “GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies,” BMC Genomics, vol. 19, no. S2, 2018. [Online]. Available: https://dx.doi.org/10.1186/s12864-018-4460-0
[5] B. Chen, F. Cai, J. Zhou, W. Ma, P. Sheridan, and W. D. Lu, “Efficient in-memory computing architecture based on crossbar arrays,” in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 17.5.1–17.5.4.
[6] P. C. Santos, F. B. Moreira, A. S. Cordeiro, S. R. Santos, T. R. Kepe, L. Carro, and M. A. Z. Alves, “Survey on near-data processing: Applications and architectures,” Journal of Integrated Circuits and Systems, vol. 16, no. 2, pp. 1–17, 2021.
[7] V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology,” in 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, pp. 273–287.
[8] S. Li, D. Niu, K. T. Malladi, H. Zheng, B. Brennan, and Y. Xie, “DRISA: A DRAM-based reconfigurable in-situ accelerator,” in 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, pp. 288–301.
[9] S. Angizi, N. A. Fahmi, W. Zhang, and D. Fan, “PIM-Assembler: A processing-in-memory platform for genome assembly,” in 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, pp. 1–6.
[10] S. Angizi and D. Fan, “REDRAM: A reconfigurable processing-in-DRAM platform for accelerating bulk bit-wise operations,” in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019, pp. 1–8.
[11] Y.-C. Kwon, S. H. Lee, J. Lee, S.-H. Kwon, J. M. Ryu, J.-P. Son, O. Seongil, H.-S. Yu, H. Lee, S. Y. Kim, Y. Cho, J. G. Kim, J. Choi, H.-S. Shin, J. Kim, B. Phuah, H. Kim, M. J. Song, A. Choi, D. Kim, S. Kim, E.-B. Kim, D. Wang, S. Kang, Y. Ro, S. Seo, J. Song, J. Youn, K. Sohn, and N. S. Kim, “25.4 A 20nm 6GB function-in-memory DRAM, based on HBM2 with a 1.2 TFLOPS programmable computing unit using bank-level parallelism, for machine learning applications,” in 2021 IEEE International Solid-State Circuits Conference (ISSCC), vol. 64, 2021, pp. 350–352.
[12] C. Sudarshan, T. Soliman, C. D. la Parra, C. Weis, L. Ecco, M. Jung, N. Wehn, and A. Guntoro, “A novel DRAM-based process-in-memory architecture and its implementation for CNNs,” in 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021, pp. 35–42.
[13] L. Wu, R. Sharifi, M. Lenjani, K. Skadron, and A. Venkat, “Sieve: Scalable in-situ DRAM-based accelerator designs for massively parallel k-mer matching,” in 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, pp. 251–264.
[14] C. Sudarshan, M. H. Sadi, C. Weis, and N. Wehn, “Optimization of DRAM based PIM architecture for energy-efficient deep neural network training,” in 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp. 1472–1476.
[15] C. Sudarshan, T. Soliman, T. Kämpfe, C. Weis, and N. Wehn, “FEFET versus DRAM based PIM architectures: A comparative study,” in 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), 2022, pp. 1–6.
[16] S. Kim, S. Kim, K. Cho, T. Shin, H. Park, D. Lho, S. Park, K. Son, G. Park, and J. Kim, “Processing-in-memory in high bandwidth memory (PIM-HBM) architecture with energy-efficient and low latency channels for high bandwidth system,” in 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2019, pp. 1–3.
[17] Z. Al-Ars, A. Van de Goor, J. Braun, and D. Richter, “A memory specific notation for fault modeling,” in Proceedings 10th Asian Test Symposium, 2001, pp. 43–48.
[18] Z. Al-Ars and A. van de Goor, “DRAM specific approximation of the faulty behavior of cell defects,” in Proceedings of the 11th Asian Test Symposium, 2002 (ATS ’02), 2002, pp. 98–103.
[19] B. Provost, T. Huang, C. Lim, K. Tian, M. Bashir, M. Atha, A. Muhtaroglu, C. Zhao, and H. Muljono, “AC IO loopback design for high speed µprocessor IO test,” in 2004 International Conference on Test, 2004, pp. 23–30.
[20] H. Jun, S. Nam, H. Jin, J.-C. Lee, Y. J. Park, and J. J. Lee, “High-bandwidth memory (HBM) test challenges and solutions,” in 2022 IEEE International Test Conference (ITC), 2022, pp. 1–10.
[21] S. Abdennadher, M. Altmann, and B. Xue, “Challenges and emerging solutions in testing HBM I/O & systems,” in 2018 IEEE 19th Latin-American Test Symposium (LATS), 2018, pp. 1–4.
[22] A.-C. Hsieh, T. Hwang, M.-T. Chang, M.-H. Tsai, C.-M. Tseng, and H.-C. Li, “TSV redundancy: Architecture and design issues in 3D IC,” in 2010 Design, Automation & Test in Europe Conference & Exhibition, 2010, pp. 166–171.
[23] K.-T. Wu, J.-F. Li, Y.-C. Yu, C.-S. Hou, C.-C. Yang, D.-M. Kwai, Y.-F. Chou, and C.-Y. Lo, “Intrachannel reconfigurable interface for TSV and micro bump fault tolerance in 3-D RAMs,” in 2014 IEEE 23rd Asian Test Symposium, 2014, pp. 143–148.
[24] Z. Al-Ars, S. Hamdioui, A. van de Goor, G. Gaydadjiev, and J. Vollrath, “DRAM-specific space of memory tests,” in 2006 IEEE International Test Conference, 2006, pp. 1–10.
[25] Y. Kang, W. Huang, S.-M. Yoo, D. Keen, Z. Ge, V. Lam, P. Pattnaik, and J. Torrellas, “FlexRAM: Toward an advanced intelligent memory system,” in 2012 IEEE 30th International Conference on Computer Design (ICCD), 2012, pp. 5–14.
[26] V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, and T. C. Mowry, “RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization,” in 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2013, pp. 185–197.
[27] S. Roy, M. Ali, and A. Raghunathan, “PIM-DRAM: Accelerating machine learning workloads using processing in commodity DRAM,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 11, no. 4, pp. 701–710, 2021.
[28] Micron Technology, Inc., “DDR3 SDRAM: System-Power Calculator,” 2016. [Online]. Available: https://www.micron.com/products/memory/dram-components/ddr3-sdram
[29] “DRAM power model,” [Online]. Available: https://www.rambus.com/energy/.
[30] N. A. Zakaria, W. Hasan, I. Halin, R. Sidek, and X. Wen, “Fault detection with optimum March test algorithm,” in 2012 Third International Conference on Intelligent Systems Modelling and Simulation, 2012, pp. 700–704.
[31] S. Hamdioui, A. van de Goor, and M. Rodgers, “March SS: A test for all static simple RAM faults,” in Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2002, pp. 95–100.
[32] M. P. D. Sai, H. Yu, Y. Shang, C. S. Tan, and S. K. Lim, “Reliable 3-D clock-tree synthesis considering nonlinear capacitive TSV model with electrical–thermal–mechanical coupling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 11, pp. 1734–1747, 2013.
[33] M. Jung, S. Panth, and S. K. Lim, “A study of TSV variation impact on power supply noise,” in 2011 IEEE International Interconnect Technology Conference, 2011, pp. 1–3.
[34] Y. Lee, D. Han, and S. Kang, “TSV built-in self-repair architecture for improving the yield and reliability of HBM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 4, pp. 578–590, 2023.
[35] Y. Uematsu, N. Ushifusa, and H. Onozeki, “Electrical transmission properties of HBM interface on 2.1-D system in package using organic interposer,” in 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 1943–1949.
[36] M. Ahmed, S. Mohapatra, and M. Chrzanowska-Jeske, “TSV- and delay-aware 3D-IC floorplanning,” Analog Integrated Circuits and Signal Processing, vol. 87, no. 1, pp. 1–17, 2016.
[37] M. A. Ahmed, S. Mohapatra, and M. Chrzanowska-Jeske, “Dynamic nets-to-TSVs assignment in 3D floorplanning,” in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1870–1873.
[38] M. Watanabe, N. Niioka, T. Kobayashi, R. Karel, M.-a. Fukase, M. Imai, and A. Kurokawa, “An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs,” in Sixteenth International Symposium on Quality Electronic Design, 2015, pp. 519–523.
[39] J.-S. Kim, C. S. Oh, H. Lee, D. Lee, H. R. Hwang, S. Hwang, B. Na, J. Moon, J.-G. Kim, H. Park, J.-W. Ryu, K. Park, S. K. Kang, S.-Y. Kim, H. Kim, J.-M. Bang, H. Cho, M. Jang, C. Han, J.-B. Lee, J. S. Choi, and Y.-H. Jun, “A 1.2 V 12.8 Gb/s 2 GB mobile wide-I/O DRAM with 4 × 128 I/Os using TSV-based stacking,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 107–116, 2012.
[40] C. Weis, N. Wehn, L. Igor, and L. Benini, “Design space exploration for 3D-stacked DRAMs,” in 2011 Design, Automation & Test in Europe, 2011, pp. 1–6.

[41] V. Nguyen, P. Christie, A. Heringa, A. Kumar, and R. Ng, “An analysis of the effect of wire resistance on circuit level performance at the 45-nm technology node,” in Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005, pp. 191–193.
[42] S. J. Bleiker, A. C. Fischer, U. Shah, N. Somjit, T. Haraldsson, N. Roxhed, J. Oberhammer, G. Stemme, and F. Niklaus, “High-aspect-ratio through silicon vias for high-frequency application fabricated by magnetic assembly of gold-coated nickel wires,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 5, no. 1, pp. 21–27, 2015.

指導教授

李進福(Jin-Fu Li)

審核日期

2024-8-21

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