使用低增益寬頻率調整範圍壓控震盪器
之1.25-GHz八相位鎖相迴路

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姓名

徐仁乾(Jen-Chien Hsu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路
(A 1.25-GHz, 8-phase phase-locked loop with low gain and wide tuning range VCO )

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摘要(中)

在這一個論文中，我們設計了兩個鎖相迴路，第一個是使用傳統電荷充放器(Charge pump)以及相位頻率偵測器(Phase frequency detector)為基本架構的鎖相迴路，操作在1.25GHz並有多相位的輸出。第二個鎖相迴路使用雙迴路架構，並使用兩個控制訊號來控制一個粗調/微調壓控震盪器，這個雙迴路的架構可以降低控制電壓雜訊所造成的時脈抖動，當雙迴路鎖相迴路在獲取狀態時，兩個迴路同時工作以達成鎖定，當鎖相迴路達到穩定時，粗調部分的迴路將會停止工作並且讓微調部分的迴路維持鎖定狀態，因為微調部分的迴路具有較小的壓控震盪器(Voltage controlled oscillator)增益，所以由控制電壓雜訊所產生的時脈抖動將會縮小。兩個鎖相迴路都可以應用在高速傳輸介面(High speed serial link)的傳送端。由模擬的結果得到第一個鎖相迴路具有6ps的時脈抖動，而第二個鎖相迴路具有3.8ps的時脈抖動。兩個鎖相迴路都可以使用台機電0.18 1P6M製程以及操作在1.8伏特。

摘要(英)

In this thesis we design two phase-locked loops. The first phase-locked loop is a traditional one which utilize charge-pump and phase-frequency detector as the basic structure. It operates at 1.25GHz with multi-phase outputs. The second phase-locked loop is a dual loop phase-locked loop using the coarse/fine tune voltage controlled oscillator and two control paths. The dual loop structure can suppress the jitter induced by the control voltage noise. When the dual loop phase-locked loop is in acquisition state, both loops are active to achieve lock. After the phase-locked loop is in the steady state, the coarse tune loop stops working and leaves the fine tune loop to maintain the lock. Because the fine tune loop has the control path with smaller VCO gain, the jitter induced by the control voltage noise will be suppressed. Both phase-locked loops can be applied in the high speed serial link transmitter. The simulation results shows that the first phase-locked loop has 6ps peak to peak jitter and the second has 3.8ps peak to peak jitter. Both phase-locked loops can be fabricated in TSMC 0.18μm 1P4M technology with 1.8V power supply voltage.

關鍵字(中)

★ 雙迴路
★ 鎖相迴路
★ 時脈抖動

關鍵字(英)

★ PLL
★ Dual Loop
★ Jitter

論文目次

Abstract i
Table of contents ii
List of Tables iv
List of Figures v
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Introduction 3
1.3 Thesis organization 3
Chapter 2 Background Study 5
2.1 Types of noise 5
2.2 Device noise analysis 8
2.3 Types of noise sources in PLL and the transfer functions 11
2.4 Methods of reducing clock jitter 12
2.4.1 Loop parameter optimization 13
2.4.2 Model improvement 13
2.4.3 System structure of phase-locked loop improvement 13
Chapter 3 1.25-GHz, 8-phase PLL design 15
3.1 Phase-locked loop design 15
3.1.1 System architecture 15
3.1.2 Phase frequency detector design 16
3.1.3 Charge pump design 19
3.1.4 Voltage controlled oscillator design 22
3.1.5 Divider design 30
3.1.6 The integration of PLL 33
3.2 Simulation result 34
3.2.1 Phase frequency detector simulation result 34
3.2.2 Charge pump simulation result 35
3.2.3 Voltage controlled oscillator simulation result 36
3.2.4 Divider simulation result 37
3.2.5 Phase-locked loop simulation result 37
3.3 Layout and testing consideration 38
Chapter 4 PLL with low gain and wide tuning range VCO 42
4.1 Motivation 42
4.2 System architecture 43
4.3 Coarse/fine tune voltage controlled oscillator 43
4.4 FSM design 45
4.5 UP/DOWN counter design 48
4.6 DAC design 48
4.7 Reset circuit design 51
4.8 Simulation result 52
4.9 Discussion 56
Chapter 5 Conclusion 57
Bibliography 58

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指導教授

蘇朝琴、劉建男
(Chau-Chin Su、Chien-Nan Liu)

審核日期

2003-7-7

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