基於自旋轉移矩磁阻式隨機存取記憶體之運算記憶體測試

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：10

、訪客IP：3.148.108.240

姓名

黃代佑(Tai-Yu Huang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

基於自旋轉移矩磁阻式隨機存取記憶體之運算記憶體測試
(Testing of STT-MRAM-Based Computing-In-Memories)

相關論文

★ 應用於三元內容定址記憶體之低功率設計與測試技術	★ 用於隨機存取記憶體的接線驗證演算法
★ 用於降低系統晶片內測試資料之基礎矽智產	★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法
★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試	★ 用於系統晶片中單埠與多埠記憶體之自我修復技術
★ 用於修復嵌入式記憶體之基礎矽智產	★ 自我修復記憶體之備份分析評估與驗證平台
★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計	★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計
★ 低功率與可自我修復之三元內容定址記憶體設計	★ 多核心系統晶片之診斷方法
★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產	★ 應用於貪睡靜態記憶體之有效診斷與修復技術
★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案	★ 應用於隨機存取記憶體之有效良率及可靠度提升技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 (2030-1-17以後開放)

摘要(中)

隨著資料密集型應用的快速發展，傳統的馮諾曼架構面臨記憶體牆問題。記憶體運算 (CIM) 架構是克服記憶體牆問題的一個很好的替代方案。CIM 架構可以以記憶體模式或運算模式運作。自旋轉移矩磁阻式隨機存取記憶體（STT-MRAM）是新興的非揮發性記憶體之一，被認為是實現 CIM 的良好候選者。為了減少 STT-MRAM 的寫入時間，提出了針對 MTJ 的替代寫入方案，即自旋霍爾輔助自旋轉移矩磁阻式隨機存取記憶體（SAS-MRAM）利用自旋軌道矩（SOT）機制來實現。本論文針對具有儲存和邏輯運算功能的基於 STT-MRAM 和 SAS-MRAM 的 CIM 進行了故障建模，並提出了March 測試來檢測儲存故障和運算故障。首先，透過為基於 1TIMTJ STT-MRAM 的CIM 架構注入單元內和單元間電氣缺陷來執行故障建模。定義了幾種記憶體和計算故障，包括靜態和動態故障。然後，提出了 18N March 測試演算法和（18 +4n1 + 2n2）N March 測試演算法來涵蓋靜態和動態故障。其次，透過為基於 2TIMTJ SAS-MRAM 的 CIM 注入單元內和單元間電氣缺陷來執行故障建模。定義了一個新的故障。然後，提出了一種 (13 +2n)N March 測試演算法來覆蓋基於 SAS-MRAM 的 CIM 的記憶體和計算故障。

摘要(英)

With the rapid development of data-intensive applications, the conventional Von Neumann architecture suffers from the memory wall problem. Computing-in-memory (CIM) architecture is one good alternative to overcome the memory wall issue. CIM architecture can be operated in memory mode or computing mode. Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the emerging non-volatile memories, which is considered as a good candidate to implement CIM. To reduce the STT-MRAM write time, alternative write scheme for MTJ is demonstrated that Spin-Hall-assisted Spin-Transfer Torque Magnetic Random Access Memory (SAS-MRAM) uses spin orbit torque (SOT) mechanism to implement. In this thesis, fault modeling is executed for STT-MRAM and SAS-MRAM-based CIMs with memory and logic operation functions, and March tests are proposed to detect memory faults and computing faults. First, fault modeling is executed by injecting intra-cell and inter-cell electrical defects for 1TIMTJ STT-MRAM-based CIM architecture. Several memory and computing faults are defined, including static and dynamic faults. Then, a 18N March test algorithm and a (18 + 4n1 + 2n2)N March test algorithm are proposed to cover static and dynamic faults. Second, fault modeling is executed by injecting intra-cell and inter-cell electrical defects for 2TIMTJ SAS-MRAM based CIMs. One new fault is defined. Then, a (13 + 2n)N March test algorithm is proposed to cover memory and computing faults of SAS-MRAM-based CIMs.

關鍵字(中)

★ 自旋轉移矩磁阻式隨機存取記憶體
★ 運算記憶體
★ 測試

關鍵字(英)

★ STT-MRAM
★ Computing-In-Memories
★ Testing

論文目次

中文摘要/Chinese abstract i
英文摘要/English abstract i
目次/Table of contents
1 Introduction 1
1.1 MRAM-based Computing-In-Memory 1
1.2 Spin-Transfer Torque Magnetic Random Access Memory 2
1.3 Spin-Hall-assisted Spin-Transfer Torque Magnetic Random Access Memory 7
1.4 Testing of Computing-In-Memories 10
1.5 Motivation 10
1.6 Contribution 11
1.7 Thesis Organization 12
2 Testing of 1T1MTJ STT-MRAM-based Computing-In-Memories 13
2.1 1T1MTJ STT-MRAM-based CIMs 13
2.2 Fault Modeling 14
2.2.1 Simulation model 14
2.2.2 Electrical Defects 19
2.2.3 Fault Modeling Flow 21
2.3 Test Development 25
2.3.1 Existing Fault Models 25
2.3.2 Pattern Dependent Faults, Computing Faults, and Dynamic Faults 26
2.3.3 Fault Analysis 31
2.3.4 Test Algorithm 39
2.4 Summary 55
3 Testing of 2T1MTJ SAS-MRAM-based Computing-In-Memories 57
3.1 2T1MTJ SAS-MRAM CIMs 57
3.2 Simulation model and Electrical Defects 57
3.2.1 Simulation model 57
3.2.2 Electrical Defects 61
3.3 Test Development 66
3.3.1 Fault Analysis 66
3.3.2 Test Algorithm 70
3.4 Summary 75
4 Conclusion and FutureWork 77
Reference 78

參考文獻

[1] T. Kawahara, K. Ito, R. Takemura, and H. Ohno, “Spin-transfer torque RAM technology: Review and prospect,” Journal of Microelectronics Reliability, vol. 52, no. 4, pp. 613–627, 2012.
[2] X. Fong, Y. Kim, R. Venkatesan, S. H. Choday, A. Raghunathan, and K. Roy, “Spin-transfer torque memories: Devices, circuits, and systems,” Proceedings of the IEEE, vol. 104, no. 7, pp. 1449–1488, 2016.
[3] Z. Wang, W. Zhao, E. Deng, J.-O. Klein, and C. Chappert, “Perpendicular-anisotropy magnetic tunnel junction switched by spin-hall-assisted spin-transfer torque,” Journal of Physics D: Applied Physics, vol. 48, no. 6, pp. 1–7, 2015.
[4] W.-J. Chen, Y.-J. Tsou, H.-C. Shih, P.-C. Liu, and C. W. Liu, “Critical current reduction of field-free perpendicular SOT-MTJ by STT assist using micromagnetic simulation,” in Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, pp. 159–162.
[5] T.-L. Tsai, J.-F. Li, C.-L. Hsu, and C.-T. Sun, “Testing of in-memory-computing 8T SRAMs,” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019, pp. 1–4.
[6] J.-F. Li, “Testing of computing memories: Faults, test algorithms, and design-for-testability,” in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, pp. 1–6.
[7] L. Wu, S. Rao, M. Taouil, G. C. Medeiros, M. Fieback, E. J. Marinissen, G. S. Kar, and S. Hamdioui, “Defect and fault modeling framework for STT-MRAM testing,” IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 707–723, 2021.
[8] S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, “Computing in memory with spin-transfer torque magnetic RAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 470–483, 2018.
[9] S. M. Nair, R. Bishnoi, M. B. Tahoori, G. Tshagharyan, H. Grigoryan, G. Harutyunyan, and Y. Zorian, “Defect injection, fault modeling and test algorithm generation methodology for STT-MRAM,” in Proceedings of IEEE International Test Conference (ITC), 2018, pp. 1–10.
[10] S. M. Nair, R. Bishnoi, A. Vijayan, and M. B. Tahoori, “Dynamic faults based hardware trojan design in STT-MRAM,” in Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE), 2020, pp. 933–938.
[11] H.-C. Chen, J.-F. Li, C.-L. Hsu, and C.-T. Sun, “Configurable 8t SRAM for enbling in-memory computing,” in Proceedings of International Conference on Communication Engineering and Technology (ICCET), 2019, pp. 139–142.
[12] A. Agrawal, A. Jaiswal, C. Lee, and K. Roy, “X-SRAM: Enabling in-memory boolean computations in CMOS static random access memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4219–4232, 2018.
[13] V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, “Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology,” in Proceedings of Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, pp. 273–287.
[14] S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, “MAGIC—memristor-aided logic,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 11, pp. 895–899, 2014.
[15] L. Xie, H. Du Nguyen, J. Yu, A. Kaichouhi, M. Taouil, M. AlFailakawi, and S. Ham- dioui, “Scouting logic: A novel memristor-based logic design for resistive computing,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017, pp. 176–181.
[16] M. Zabihi, A. K. Sharma, M. G. Mankalale, Z. I. Chowdhury, Z. Zhao, S. Resch, U. R. Karpuzcu, J.-P. Wang, and S. S. Sapatnekar, “Analyzing the effects of interconnect parasitics in the STT CRAM in-memory computational platform,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp. 71-79, 2020.
[17] Z. He, S. Angizi, and D. Fan, “Exploring STT-MRAM based in-memory computing paradigm with application of image edge extraction,” in Proceedings of IEEE International Conference on Computer Design (ICCD), 2017, pp. 439–446.
[18] S. Jung, H. Lee, S. Myung, H. Kim, S. K. Yoon, S.-W. Kwon et al., “A crossbar array of magnetoresistive memory devices for in-memory computing,” Journal of Nature, vol. 601, no. 7892, pp. 211–216, 2022.
[19] D. Fan and S. Angizi, “Energy efficient in-memory binary deep neural network accelerator with dual-mode SOT-MRAM,” in Proceedings of IEEE International Conference on Computer Design (ICCD), 2017, pp. 609–612.
[20] Z. He, S. Angizi, F. Parveen, and D. Fan, “High performance and energy-efficient in-memory computing architecture based on SOT-MRAM,” in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2017, pp. 97–102.
[21] T. Kim, Y. Jang, M.-G. Kang, B.-G. Park, K.-J. Lee, and J. Park, “SOT-MRAM digital PIM architecture with extended parallelism in matrix multiplication,” IEEE Transactions on Computers, vol. 71, no. 11, pp. 2816–2828, 2022.
[22] Z. Guo, J. Yin, Y. Bai, D. Zhu, K. Shi, G. Wang, K. Cao, and W. Zhao, “Spintronics for energy-efficient computing: An overview and outlook,” Proceedings of the IEEE, vol. 109, no. 8, pp. 1398–1417, 2021.
[23] A. V. Khvalkovskiy, D. Apalkov, S. Watts, R. Chepulskii, R. Beach, A. Ong et al., “Basic principles of STT-MRAM cell operation in memory arrays,” Journal of Physics D: Applied Physics, vol. 46, no. 7, pp. 1–22, 2013.
[24] Q. Shao, P. Li, L. Liu, H. Yang, S. Fukami, A. Razavi, H. Wu, K. Wang, F. Freimuth, Y. Mokrousov, M. D. Stiles, S. Emori, A. Hoffmann, J. A? kerman, K. Roy, J.-P. Wang, S.-H. Yang, K. Garello, and W. Zhang, “Roadmap of spin–srbit torques,” IEEE Transactions on Magnetics, vol. 57, no. 7, pp. 1–39, 2021.
[25] Y. Zhang, X. Wang, Y. Li, A. Jones, and Y. Chen, “Asymmetry of MTJ switching and its implication to STT-RAM designs,” in Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 1313–1318.
[26] L. Wu, M. Taouil, S. Rao, E. J. Marinissen, and S. Hamdioui, “Survey on STT-MRAM testing: Failure mechanisms, fault models, and tests,” ArXiv, vol. abs/2001.05463, 2020.
[27] M. Dyakonov and V. Perel, “Current-induced spin orientation of electrons in semiconductors,” Journal of Physics Letters A, vol. 35, no. 6, pp. 459–460, 1971.
[28] J. Sinova, S. O. Valenzuela, J. Wunderlich, C. H. Back, and T. Jungwirth, “Spin hall effects,” Journal of Rev. Mod. Phys., vol. 87, pp. 1213–1260, 2015.
[29] V. Edelstein, “Spin polarization of conduction electrons induced by electric current in two-dimensional asymmetric electron systems,” Journal of Solid State Communications, vol. 73, no. 3, pp. 233–235, 1990.
[30] A. Chintaluri, H. Naeimi, S. Natarajan, and A. Raychowdhury, “Analysis of defects and variations in embedded spin transfer torque (STT) MRAM arrays,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 319–329, 2016.
[31] S. M. Nair, C. Mu‥nch, and M. B. Tahoori, “Defect characterization and test generation for spintronic-based compute-in-memory,” in Proceedings of IEEE European Test Symposium (ETS), 2020, pp. 1–6.
[32] J. Kim, A. Chen, B. Behin-Aein, S. Kumar, J.-P. Wang, and C. H. Kim, “A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies,” in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), 2015, pp. 1–4.
[33] K. Monga, L. Maheshwari, N. Chaturvedi, and S. Gurunarayanan, “Twin-coupled sense amplifier to improve margin in 1T-1MTJ based MRAM array,” in Proceedings of International Symposium on VLSI Design and Test (VDAT), 2020, pp. 1–4.
[34] R. Bishnoi, M. Ebrahimi, F. Oboril, and M. B. Tahoori, “Read disturb fault detection in STT-MRAM,” in Proceedings of International Test Conference, 2014, pp. 1–7.
[35] Y.-X. Chen and J.-F. Li, “Fault modeling and testing of 1T1R memristor memories,” in Proceedings of IEEE VLSI Test Symposium (VTS), 2015, pp. 1–6.
[36] Y. C. Yang and J.-F. Li, “Fault modeling and testing of RRAM-based computing-in memories,” in Proceedings of IEEE International Test Conference in Asia (ITC-Asia), 2022,
pp. 7–12.

指導教授

李進福(Jin-Fu Li)

審核日期

2025-1-20

推文