應用於光耦合隔離系統之發送端三角積分調變器

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姓名

李侑光(You-Guang Li) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於光耦合隔離系統之發送端三角積分調變器
(A Design of Sigma Delta Modulator for Optical Coupling Isolation Applications)

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摘要(中)

隨著科技不斷進步，我們正步入第四次工業革命，也就是工業4.0時代。其核心聚焦於互聯性、自動化、機器學習等領域。透過智能技術、演算法以及對機械設備的控制，為自動化的監控與分析技術帶來了全新突破。近年來的工業控制產品，對效率與精度提出了更高的要求。在工業設備中，測量物理傳感器信號的精確度是控制系統的核心之一。從測量的角度來看，不僅需要確保最高的精度，還必須維持安全性與可靠性。此外，由於工業控制系統經常在高危險電壓下運行，因此需要廣泛使用隔離器來保護操作人員與周邊的電子設備。本電路旨在以高精度和低功耗為設計目標，開發適用於隔離器的類比數位轉換器。
本論文實現一應用於光耦合隔離系統之發送端類比數位轉換器，於高壓與低壓應用環境皆使用之類比數位轉換器主要由三角積分調變器(Sigma-Delta Modulator, SDM)與數位降頻率波器組成。整體架構採用切換式電容開關實現，其內部電路使用浮動反向式放大器(Floating Inverter Amplifier, FIA)實現離散時間積分器，並以一四位元非同步SAR ADC實現量化器，於提高解析度的同時降低功耗。
本電路採用台積電T18HVG2與TSMC 0.18μm CMOS 1P6M製程，晶片面積分別約佔1.567 mm2與1.227 mm2，電源供應電壓分別為5V與1.2V，整體電路功耗分別為15.87 mW與100.5 μW，電路頻寬皆為40 kHz，電路取樣頻率分別為20.48 MHz與5.12 MHz，有效位元數分別為12與14 位元。

摘要(英)

As technology continues to advance, we are stepping into the era of the Fourth Industrial Revolution, also known as Industry 4.0. The key focus areas include connectivity, automation, machine learning, and related domains. By utilizing intelligent technologies, algorithms, and control over mechanical devices, significant breakthroughs have been achieved in automated monitoring and analysis. In recent years, industrial control products have demanded higher efficiency and precision. Accurate measurement of physical sensor signals is one of the core elements of control systems in industrial equipment. From a measurement perspective, it is critical to ensure not only the highest level of accuracy but also safety and reliability. Additionally, since industrial control systems often operate under high-voltage conditions, isolators are widely employed to protect operators and adjacent electronic devices. This circuit aims to develop an analog-to-digital converter (ADC) for isolators, with high precision and low power consumption as the design goals.
This thesis presents the implementation of a transmitter-side ADC for optocoupler isolation systems. The ADC, suitable for both high-voltage and low-voltage applications, mainly consists of a Sigma-Delta Modulator (SDM) and a digital decimation filter. The overall architecture is realized using a switched-capacitor design, where a floating inverter amplifier (FIA) is employed to implement the discrete-time integrator. Additionally, a 4-bit asynchronous SAR ADC is used as the quantizer to enhance resolution while reducing power consumption.
The circuit is fabricated using T18HVG2 and TSMC′s 0.18μm CMOS 1P6M process, with chip areas of approximately 1.567 mm2 and 1.227 mm2. The supply voltages are 5V and 1.2V, with total power consumptions of 15.87 mW and 100.5 μW, respectively. The bandwidth of these circuits is 40 kHz, and the sampling frequencies are 20.48 MHz and 5.12 MHz, respectively. The resolutions are 12-bits and 14-bits, respectively.

關鍵字(中)

★ 類比數位轉換器
★ 三角積分調變器
★ 浮動反向式放大器
★ 連續漸進式類比數位轉換器

關鍵字(英)

★ Analog-to Digital Converter
★ Sigma-Delta Modulator
★ Floating Inverter Amplifier
★ SAR ADC

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 xi
第一章緒論 1
1.1 背景 1
1.2 研究動機 3
1.3 論文貢獻 4
第二章三角積分調變器原理概論 5
2.1 奈奎斯特與超取樣類比數位轉換器 5
2.2 量化誤差 8
2.3 超取樣技術與雜訊移頻技術 10
2.3.1超取樣技術 10
2.3.2雜訊移頻技術 12
2.4三角積分調變器 14
2.4.1一階三角積分調變器 14
2.4.2 二階三角積分調變器 16
2.4.3 高階三角積分調變器 17
第三章類比數位轉換器設計與模擬 19
3.1 二階回授型三角積分調變器 21
3.1.1 二階回授型三角積分調變器規格訂製 21
3.1.2 二階回授型三角積分調變器系統設計 21
3.1.3 電路非理想效應考量 23
3.1.4 電路設計 34
3.1.5 佈局前模擬結果 41
3.2 二階前饋型三角積分調變器 44
3.2.1 二階前饋型三角積分調變器規格訂製 45
3.2.2 二階前饋型三角積分調變器系統設計 46
3.2.3 電路非理想效應 47
3.2.4 電路設計 49
3.2.5 佈局前模擬結果 58
第四章佈局考量與模擬結果 62
4.1 二階回授型三角積分調變器 62
4.1.1 佈局平面圖 62
4.1.2 佈局後模擬結果 64
4.2 二階前饋型三角積分調變器 65
4.2.1 佈局平面圖 65
4.2.2 佈局後模擬結果 67
第五章量測規劃與考量 70
5.1 二階回授型三角積分調變器 70
5.1.1 量測規劃 70
5.1.2 量測結果 71
5.2 二階前饋型三角積分調變器 74
5.2.1 量測規劃 74
第六章結論與未來展望 75
6.1 文獻比較 75
6.1.1 二階回授型三角積分調變器 75
6.1.2 二階前饋型三角積分調變器 76
6.2 未來展望 78
參考文獻 79

參考文獻

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2025-3-21

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