應用於矽製程的去嵌入技術、電感及接觸墊之研究

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：101

、訪客IP：18.226.185.44

姓名

楊渝澤(Yu-Ze Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於矽製程的去嵌入技術、電感及接觸墊之研究
(The Study on the Application of De-embedding Techniques, Inductors and Pads in Silicon Process)

相關論文

★ 應用於筆記型電腦數位電視單極天線之研製	★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計	★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究	★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究	★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製
★ 應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製	★ 應用於K / V 頻段低功耗混頻器之研製
★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究	★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製
★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製	★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製
★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製	★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

摘要
本論文主題在於以現有的矽基板製程(CMOS、SiGe)來對於去嵌入技術、螺旋型電感以及接觸墊的寄生效應作一探討。冀望於此探討中，得到最佳的去嵌入機制，以獲得最準確之元件量測結果。同時在電感方面，能夠擁有最佳的品質因數和自振頻率的電感。最後，希望能得到寄生效應最為微弱，卻又能不造成量測困擾的接觸墊。
第一部份是介紹去嵌入機制，將目前較常為人所用的去嵌入機制分別敘述，並以量測結果作一比較，從中找出一最方便、最精準的方式，最後得到的結果，是以接地屏蔽層去嵌入機制所得到的數據最佳。第二部分是探討目前所使用的螺旋型電感，從最基本的電感原理著手，再延伸至目前於矽製程上所使用的螺旋型電感。包括電感的寄生效應、元件模型、品質因數及其改善方法。最後，利用不同的規格的電感做量測，並比較電感值和品質因數的差異。其結果是利用矽鍺製程中的格狀深溝槽屏蔽的方式，可獲得最佳的品質因數，且仍能維持電感原有的特性。第三部分討論的是接觸墊的寄生效應及其改進方法。文中利用防護圈的方式，可有效的降低電阻性的損耗，使得基板效應降低。
由於在矽製程上射頻電路的實現，使得設計者對於製程的要求，無論是製程特性，或是元件模型的準確度都越來越高。然而，矽製程仍然有其限制存在。因此，如何利用現有的製程，在不增加製作成本的前提下，使所設計的電路發揮最大效能，仍是一個需要努力的目標。

摘要(英)

Abstract
The purpose of this thesis studies on the de-embedded techniques applied in silicon base processes, such as CMOS and Silicon-Germanium technologies, the de-embedding techniques, parasitic effects, spiral inductors, and PADs will be discussed in detail. The spiral inductor designs are investigated with different shielding techniques. The quality factor Q and self-resonant frequency are the figure of merit of these inductor designs. The inductor with mesh deep trench shielding achieved the best quality factor and highest self resonant frequency. Finally, a PAD model is investigated and the equivalent circuit model is presented up to 20 GHz.
The first part in this thesis is to introduce the de-embedding structure. Several de-embedding methods are introduced and given some meaningful comparisons. The completed de-embedding techniques and parameter extraction procedures are presented using straightforward mathematic calculations. The ground-shield de-embedding structure obtains the best results among the others methods. A small signal device model of CMOS is demonstrated by using these techniques. The second part is the study of spiral inductors. The basic inductance principle is first introduced. Modern planar spiral inductor used on the silicon-based technology is then studied including its parasitic effects, device model, quality factor and the method of improving. Finally, compare the difference with inductance value and quality factor by the measurement of inductors with different specifications. The inductor with mesh deep trench shield in silicon germanium obtains the best quality factor. The third part discussion is the parasitic effect of the PAD and improving method of PAD is proposed. Using the guard ring can reduce the resistance loss and the substrate effects effectively.
Since the implementation of radio frequency circuits on silicon plays very important role in the recent novel emerging applications, the request for precise processes, accuracy device models get more and more important. However, the silicon process still has existence of limiting. It’s a goal to use existing process under the major premise of maintaining the cost of manufacture which makes the circuit design accomplish the greatest efficiency.

關鍵字(中)

★ 去嵌入
★ 接觸墊
★ 電感

關鍵字(英)

★ Inductors
★ De-embedding
★ PADs

論文目次

第一章緒論
§1-1 簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧01
§1-2 章節概要‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧02
第二章應用於矽製程的去嵌入機制
§2-1 簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧03
§2-2 架構概述‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧03
§2-2-1 開路去嵌入機制‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧03
§2-2-2 三步驟去嵌入機制‧‧‧‧‧‧‧‧‧‧‧‧‧‧05
§2-2-3 四步驟去嵌入機制‧‧‧‧‧‧‧‧‧‧‧‧‧‧08
§2-3 接地屏蔽層去嵌入機制‧‧‧‧‧‧‧‧‧‧‧‧‧‧13
§2-4 量測結果與比較‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧18
§2-5 結論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧22
第三章矽製程的電感元件之特性
§3-1 簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧23
§3-2 原理概述‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧23
§3-3 電感元件上之寄生效應及損耗‧‧‧‧‧‧‧‧‧‧‧25
§3-3-1 金屬損耗‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧25
§3-3-1-1 片電阻‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧26
§3-3-1-2 渦狀電流‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧26
§3-3-2 基板損耗‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧27
§3-3-2-1 電場穿透‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧27
§3-3-2-2 磁場損耗‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧28
§3-4 電感模型及品質因數‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧28
§3-5 強化品質因數的方法‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧32
§3-5-1 改善電感的佈局‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧32
§3-5-2 改善電感所用的金屬‧‧‧‧‧‧‧‧‧‧‧‧‧33
§3-5-3 使用高阻抗基板‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧34
§3-5-4 圖形式接地屏蔽‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧35
§3-6 格狀深溝槽式‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧36
§3-7 量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧38
§3-8 結論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧43
第四章在矽製程中的接觸墊及其效應
§4-1 簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧44
§4-2 架構簡述‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧44
§4-3 接觸墊寄生效應及改善‧‧‧‧‧‧‧‧‧‧‧‧‧‧45
§4-4 量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧46
§4-5 結論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧50
第五章結論與未來工作‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧52
參考文獻‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧53
附錄A 各種參數之間的轉換‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧55
附錄B 電路的T模型和π模型‧‧‧‧‧‧‧‧‧‧‧‧‧‧58

參考文獻

[1] H. Cho and D. E. Burk, “A Three-Step Method for the De-Embedding of High-Frequency S-Parameter Measurements,” IEEE Transactions on Electron Devices, vol. 38, no. 6, pp. 1371–1375, June 1991.
[2] T. E. Kolding, “A 4-Step Method for De-Embedding Gigahertz On- Wafer CMOS Measurements,” To appear in IEEE Transactions on Electron Devices in 2000
[3] Troels Emil Kolding, Ole Kiel Jensen, and Torben Larsen, “Ground-Shielded Measuring Technique for Accurate On-Wafer Characterization of RF CMOS Devices” IEEE international conference on Microelectronic Test Structure, March 2000,
[4] Chung-HuiChen,Yean-KuenFang,Chih-WeiYang,andC.S.Tang, “A Deep Submicron CMOS Process Compatible Suspending High-Q Inductor,” IEEE Electron Device Letters, vol.22, no.11, November 2001
[5] Belinda Piernas, Kenjiro Nishikawa, and Kenji Kamogawa “High-Q Factor Three-Dimensional Inductors,” IEEE Transactions on Microwave Theory and Techniques, vol.50, no.8, August 2002
[6] Mina Danesh, John R. Long, R. A. Hadaway, and D. L. Harame, “A Q-Factor Enhancement Technique for MMIC Inductors,” IEEE MTT-S Int. Microwave Symp. Dig, 1998, pp. 169-172
[7] C. Patrick Yue and S. Simon Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s,” IEEE Journal of Solid-State Circuits, vol.33, no.5, May 1998
[8] C. Patrick Yue and S. Simon Wong, “Physical Modeling of Spiral Inductors on Silicon,” IEEE Transactions on Electron Devices vol.47, no.3, March 2000
[9] Seong-Mo Yim, Tong Chen, and Kenneth K. O, “The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors,” IEEE Journal of Solid-State Circuits, vol.37, no.2, February 2002
[10] Inder Bahl, “Lumped Elements for RF and Microwave Circuits” Artech House
[11] Ali M. Niknejad, “Analysis, Simulation, and Applications of Passive Devices on Conductive Substrates” University of California at Berkeley, Spring 2000
[12] Thomas H. Lee, “The Design of CMOS Radio-frequency Integrated Circuits,” Cambridge University Press
[13] A. O. Adan, M. Fukumi, K. Hagashi, T. Suyama, M. Miyamoto, and M.Hayashi, “Electromagnetic Coupling Effects in RFCMOS Circuits,” IEEE Radio Frequency Integrated Circuits Symposium
[14] Ming-Dou Ker, Hsin-Chin Jiang, and Chyh-Yih Chang, “Design on the Low-Capacitance Bond Pad for High-Frequency I/O Circuits in CMOS Technology,” IEEE Transactions on Electron Devices vol.48, no.12, December 2001
[15] Ming-Dou Ker, and Jeng-Jie Peng, “Fully Process-Compatible Layout Design on Bond Pad to Improve Wire Bond Reliability in CMOS Ics,” IEEE Transactions on Components and Packaging Technologies, vol. 25, no. 2, June 2002
[16] Natalino Camilleri, Jim Kirchgessner, Julio Costa, David Ngo and David Lovelace, “Bonding Pad Models for Silicon VLSI Technologies and Their Effects on the Noise Figure of RF NPNs” IEEE MTT-S Digest, 1994
[17] Guillermo Gonzalez, “Microwave Transistor Amplifiers,” Prentice Hall
[18] Wang Qingping, Zhang Zhengfan, Li Kaicheng, Guo Lin, Xiangdong Wu, and Wang Zihang, “A Deep Trench Isolation for Silicon” Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on , 21-23 Oct. 1998 Pages:172 – 175
[19] Cheon Soo Kim, Piljae Park, Joung-Woo Park, Nam Hwang, and Hyu Kyu Yu, “Deep Trench Guard Technology to Suppress Coupling between Inductors in Silicon RF Ics” Microwave Symposium Digest, 2001 IEEE MTT-S International , Volume: 3 , 20-25 May 2001 Pages:1873 - 1876 vol.3
[20] H. Yoshida, H. Suzuki, Y. Kinoshita, H. Fujii, T. Yamazaki, “An RF BiCMOS Process using High fSR Spiral Inductor with Premetal Deep Trenches and A Dual Recessed Bipolar Collector Sink,” Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International , 6-9 Dec. 1998 Pages:213 - 216

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2004-10-30

推文