遞迴式類神經網路應用於序向電路之高階功率模型的研究

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姓名

薛智杰(Jhih-Jie Syue) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

遞迴式類神經網路應用於序向電路之高階功率模型的研究
(On High-Level Power Modeling Using Recurrent Neural Networks for Sequential Circuits)

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摘要(中)

現今，由於晶片密度與操作頻率的增加，導致在IC設計中去考慮功率消耗變成是一個非常重要的問題。為了避免在IC設計過程中需要額外花費時間的重新設計流程，能在IC設計初期準確預估出所需功率消耗，是一件很重要的事。
預估序向電路與組合邏輯電路的功率消耗相比之下，序向電路被公認困難的多.原因是因為序向電路的功率通常在內部的狀態與輸入向量之間有一定程度上的時間關係。即使在傳統研究中，也很難描述出此類影響。基於這個理由，我們提出了一種方法，利用遞迴式類神經網路來建立序向電路的功率模型.此方法主要是去學習輸入ˋ輸出訊號間的統計數值與相對應的消耗功率。而遞迴式類神經網路具有內部的遞迴連結，我們希望透過此連結來降低訊號間的相依關係。
與傳統研究不同的是，我們的功率模型不但具有能自動調整功率分佈的非線性特徵與輸入序列間的相依關係，而且複雜度還相當的低。更重要的是，我們的類神經網路不需要低階的電路資訊，所以非常適合IP保護的特性。由實驗的結果可以看出即使在很短的輸入序列長度(50筆)，我們的功率模型也能提供相當不錯的準確度。換句話說，我們所提的模型能廣泛的使用在不同應用上。

摘要(英)

Nowadays, the increasing in chip density and operating frequency have also made power dissipation a critical problem during IC design. In order to avoid costly redesign steps in IC design process, accurately estimate power dissipation on high-level of abstract is very important and necessary.
In sequential circuits, power estimation is considerably more difficult than combinational circuits, because the power dissipation also depend on internal states and strong temporal correlations often exist in the input sequences, which are also hard to handle their effects in traditional approaches. For this reason, we propose a novel power model for CMOS sequential circuits by using recurrent neural networks (RNNs) to learn the relationship between input/output signal statistics and the corresponding power dissipation, because the RNNs has the internal feedback to handle temporal correlations.
Unlike traditional approach of power estimation (for example: building lookup table), not only our neural power model automatically consider the non-linear characteristic of power distributions and the temporal correlation of the input sequences but also has very low complexity.
More importantly, using our neural power model for power estimation does not require any transistor-level or gate-level description of the circuits. So it is suitable for IP protection. The experiment results have shown that the estimations are still accurate even for short sequence with only 50 pattern-pairs. It shows that our power model can be used in various applications.

關鍵字(中)

★ 類神經
★ 功率模型

關鍵字(英)

★ neural
★ power model

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 4
Chapter 2 Related Works 5
2.1 Power Consumption of CMOS Digital Circuits 5
2.2 Overview of Power Estimation Techniques 6
2.3 High-Level Power Estimation Techniques 7
2.4 Existing Power Models for Sequential Circuits 11
2.5 Power Estimation Using Neural Networks 13
2.6 Summary 14
Chapter 3 Artificial Neural Network 15
3.1 Introduction 15
3.2 Biological Neurons VS. Artificial Neurons 16
3.3 Elman Neuronal Network 18
3.4 Training Algorithms 19
3.5 The Properties of Neural Network 21
3.6 Summary 22
Chapter 4 Power Modeling with Neural Network 23
4.1 Introduction 23
4.2 Power Model Construction 24
4.3 Parameters of Neural Network 25
4.3.1 Input Data Type 25
4.3.2 Number of Hidden Neurons 29
4.3.3 Design Training Sets 31
4.4 Power Estimation with the Neural Model 31
4.5 Summary 33
Chapter 5 Experimental Results 34
Chapter 6 Conclusions 38

參考文獻

[1] F. Najm, “A survey of power estimation techniques in VLSI circuits,” IEEE Trans. VLSI Syst., vol. 2, pp. 446-455, Dec. 1994
[2] P. Landman, “High-Level Power Estimation”, IEEE Proc. of ISLPED, Monterey, CA, pp. 29-35, June 1996.
[3] E. Macii, M. Pedram, F. Somenzi, “High-Level Power Modeling, Estimation, and Optimization”, IEEE Transactions on CAD, vol. 17, pp. 1061-1079, Aug. 1998.
[4] Subodh Gupta and Farid N. Najm. “Power Modeling for High-Level Power Estimation,” IEEE Transactions on VLSI Systems, pp. 18-29, Feb. 2000.
[5] Roberto Corgnati, Enrico Macii and Massimo Poncino, “Clustered Table-Based Macromodels for RTL Power Estimation,” in Proceeding of 9th Great Lakes Symposium on VLSI, pp. 354-357, 1999.
[6] Alessandro Bogliolo, Roberto Corgnati, Enrico Macii and Massimo Poncino, “Parameterized RTL Power Models for Soft Macors,” IEEE Transactions on VLSISystems, pp. 880-887, Dec. 2001.
[7] Sudodh Gupta, Farid N. Najm, “Analytical models for RTL Power Estimation of Combinational and Sequential circuits”, IEEE Transactions on CAD, vol. 19, pp. 808-814, July 2000.
[8] Qing Wu, Qinru Qiu, Massoud Pedram, and Chih-Shun Ding, “Cycle-Accurate Macro-Models for RT-Level Power Analysis”, IEEE Transactions on VLSI Systems, vol. 6, pp. 520-528, Dec. 1998.
[9] Sudodh Gupta and Farid N. Najm, “Energy-Per-Cycle Estimation at RTL”, in Proceeding of ACM/IEEE Internal Symposium on Low Power Design, pp. 121-126, 1999.
[10] Lipeng Cao, “Circuit Power Estimation Using Pattern Recognition Techniques”, IEEE/ACM International Conference on Computer-Aided Design, pp. 412-417, 2002.
[11] Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, and Jing-Yang Jou, "A Tableless Approach for High-Level Power Modeling Using Neural Network," submitted to IEEE Transactions on Computer-Aided Design. (under revision)
[12] Freitas A.T. and Oliveira A.L., “Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation”, Design, Automation and Test in Europe Conference and Exhibition, pp. 764-769, 2003.
[13] G. Hachtel, E. Macii, A. Pardo, and F. Somenzi. “Markovian analysis of large finite state machines,” IEEE Transactions on Computer-Aided Design, Dec. 1996.
[14] D. Brand and C. Visweswariah, “Inaccuracies in power estimation during logic synthesis,” in Proc. Int. Conf. Computer-Aided Design, 1996, pp. 388–39
[15] Huzefa Mehta, Robert Michael Owens and Mary Jane Irwin, “Energy Characterization based on Clustering”, Proceeding of 33rd Design AutomationConference, PP.702-707,1996
[16] Jiing-Yuan Lin, Wen-Zen Shen, and Jing-Yang Jou, “A Structure-Oriented Power Modeling Technique for Macrocells”, IEEE Transactions on VLSI Systems, pp.380-391, Sep. 1999
[17] Chih-Yang Hsu and Wen-Zen Shen, “Vector Compaction for Power Estimation with Grouping and Consecutive Sampling Techniques”, Proceeding of International Symposium on Circuits and Systems, vol. II, pp. 472-475, 2002.
[18] Enrico Macii and Massirno Poncino. “Estimating Power Consumption of CMOS Circuits Modelled as Symbolic neural networks,” IEE Proceedings on Computers and Digital Techniques, pp. 331-336, Sep. 1996.
[19] J.H. HOPFIELD, “Artificial neural networks”, IEEE Circuits and Devices Mag., pp. 3-10, Sep. 1988.
[20] R.I. Bahar, E.A. Frohm, C.M. Gaona, G.D. Hachtel, E. Macii, A. Pardo, and F. Somenzi, “Algebraic decision diagrams and their applications”, IEEE/ACM International Conference on Computer-Aided Design, pp. 188-191, 1993.
[21] Jacek M. Zurada, “Introduction to Artificial Neural Systems”, WEST PUBLISHING COMPANY, 1992.
[22] Martin T. Hagan, Howard B. Demuth, Mark Beale, “Neural Network Design”, PWS Publishing Company, 1995.
[23] Michael Chester, “Neural Networks – A Tutorial”, PTRPrentice Hall 1993
[24] Elman, J. L., “Finding structure in time”, Cognitive Science, vol. 14, pp. 179-211, 1990.
[25] S. Chowdhury and J. S. Barkatullah, “Estimation of maximum currents in MOS IC logic circuits,” IEEE Transactions on Computer-Aided Design, vol. 9, no. 6, pp. 642-654, June 1990
[26] Farid N. Najm, “Power Estimation Techniques for Integrated Circuits”, Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on , Nov. 1995
[27] Christopher M. Bishop, “Neural Networks for Pattern Recognition”, Oxford University Press Inc., 1995.
[28] Kishan Mehrotra, Chilukuri K. Mohan and Sanjay Ranka, “Elements of Artificial Neural Networks,” Cambridge, Massachusetts: MIT Press, 1997.
[29] Eric B. Baum and David. Haussler, “What Size Net Gives Valid Generalization?” Neural Computation, Vol. 1, pp. 151-160, 1989.
[30] Joseph N. Kozhaya, Farid N. Najm. “Accurate power estimation for large sequential circuits” Computer-Aided Design, 1997.
[31] Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang. ”Statistical Estimation of Average Power Dissipation In Sequential Circuits” Design Automation Conference, 1997.

指導教授

劉建男(Chien-Nan Liu)

審核日期

2004-7-12

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