具有適應性終端電阻及預先增強器之8Gbps串列連結傳送器

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姓名

陳志寧(Chih-Ning Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具有適應性終端電阻及預先增強器之8Gbps串列連結傳送器
(8Gbps Serial Link Transmitter with Adaptive Termination Resistors and Pre-Emphasis)

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摘要(中)

由於多媒體應用的增加，使得傳輸資料頻寬的需要量增大。如果把高速串列連結傳輸應用在價格低廉的纜線上，將是非常節省成本的方法。本論文中，我們實現所提出之平行化打散器(Parallel Scrambler)，以及完成高速串列連結之資料傳送器並且建構適應性終端電阻與信號預先增強器電路於其中，來實際應用在高速傳輸上。並且提出一平行化打散器之設計法則與架構，把串列化打散器轉換成任意之平行輸出以解決在速度上的限制，達到速度上之要求。而在電路設計上，提出一新型具互斥或運算(Exclusive OR)之正負緣觸發暫存器使得打散器可以操作在更高的工作頻率。經由量測，證明使用TSMC 0.18um 1P6M CMOS製程製作之平行化打散器，可以工作在40Gbps的速度。
接著說明此高速串列連結之資料傳送器架構。提出一適應性終端電阻與架構，可以針對不同纜線的特性阻抗自動地調整成和它一樣，讓輸出端對傳輸電纜75Ω~45Ω的特性阻抗值做到匹配的效果，使訊號不會因阻抗不匹配產生反射。此外，改進了調整預先增強器電流的架構，讓預先增強器可以操作的更容易。此完整的高速串列連結之資料傳送器可以應用在長度為1公尺至15公尺的纜線上，在5公尺纜線下傳輸速率可達8Gbps，整個電路以TSMC 0.18um 1P6M CMOS製程予以實現。

摘要(英)

Due to the increasing requirement of multimedia applications, the demand for data transmission bandwidth is increased. It is very efficient to make the use of low cost coaxial cable for high-speed link transmitting.In this thesis, we will implement a parallel scrambler and a high-speed serial link transmitter with adaptive termination resistors and pre-emphasis. A very systematic parallel scrambler design methodology and architecture is proposed to overcome the limitation of serial scrambler. A new XOR-DET-C2MOS cell is proposed to speed up the operation speed of the parallel scrambler. Measurement results show that 40Gbps parallel scrambler with 16 outputs can be achieved by using 0.18um CMOS process.
We also propose a digital approach of adaptive termination resistors and architecture in the transmitter. It can match the characteristic impedance of coaxial cable automatically from 75Ω~45Ω to reduce the reflection caused by the mismatch of impedance. Moreover, the architecture of pre-emphasis is improved to make the method of tuning pre-emphasis current more easy. The transmitter with pre-emphasis can handle coaxial cable length from 1-meter to 15-meter. The performance of transmitting data at 8Gbps over the 5-meter coaxial cable is achieved. The overall circuit is implemented in TSMC 0.18um 1P6M process.

關鍵字(中)

★ 預先增強傳送器
★ 平行化打散器
★ 終端電阻

關鍵字(英)

★ Transmitter with Pre-emphsis
★ Termination Resistors
★ Parallel Scrambler

論文目次

Contents
Chapter1 Introduction 1
1.1 Introduction to High-Speed Serial Link Transmitter 1
1.1.1 System Overview 2
1.1.2 Transmitter Architecture Overview 3
1.2 Motivation and Goals 5
1.3 Thesis Organization 7
Chapter2 Overview of Scrambler 8
2.1 Introduction of Serial Scrambler 8
2.2 The Advantages of Scrambling 12
2.2.1 Spread the Spectrum 12
2.2.2 Data Transitions 14
2.2.3 Encryption 15
2.3 The Bit-Shift Parallel Scrambler 15
2.4 Summary 16
Chapter3 Parallel Scrambler Algorithm and Circuit Implementation 18
3.1 Overview 18
3.2 The Proposed Parallel Scrambler Algorithm 20
3.3 The Circuit Design of Parallel Scrambler 26
3.3.1 Double Edge-Triggered TSPC/C2MOS Register 26
3.3.2 The Proposed XOR-DET-C2MOS Register 27
3.3.3 Comparisons of The Circuit Design 29
3.4 Chip Implementation 29
3.4.1 Architecture and Measurement Consideration 29
3.4.2 Layout and Simulation Results 31
3.5 Measurements and Comparisons 33
3.6 Summary 36
Chapter4 Adaptive Termination Resistors 38
4.1 Introduction of Termination Methods 38
4.2 On-Chip Resistor Design 40
4.2.1 Parallel Resistors Architecture 41
4.2.2 Circuit Design 42
4.3 Adaptive Termination Architecture 43
4.3.1 Conventional Analog Approach 43
4.3.2 Proposed Digital Approach 44
4.4 Adaptive Termination Circuit Design 46
4.4.1 Control Logic Circuit 46
4.4.2 Comparator 47
4.5 Simulation Results and Comparisons 48
4.6 Summary 50
Chapter5 Transmitter with Pre-Emphasis 51
5.1 Introduction 51
5.2 Pre-emphasis Architecture of Transmitter 52
5.3 Circuit Design 54
5.3.1 PRBS Generator 55
5.3.2 Data Synchronizer 55
5.3.3 Parallel In Serial Out Multiplexer 56
5.3.4 Output Driver 58
5.4 Simulation Results and Comparison 58
5.5 Measurement Consideration 62
5.6 Summary 63
Chapter6 Conclusions 64
Bibliography 66

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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2004-7-17

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