數位有限脈衝響應多階多速率之濾波器/降頻器/升頻器設計及其模組產生器

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姓名

陳筱筠(Hsiao-Yun Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

數位有限脈衝響應多階多速率之濾波器/降頻器/升頻器設計及其模組產生器
(Multirate Multistage Digital FIR Filter / Decimator / Interpolator Module Generator)

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摘要(中)

在本篇論文中，我們實現了一個數位有限脈衝響應多階多速率之濾波器/降頻器/升頻器模組產生器。使用者能夠藉由此產生器，自動設計出高速低複雜度的數位有限脈衝響應多階多速率濾波器。此產生器利用線性相位濾波器的對稱性架構，並運用多階多速率IFIR濾波器的方法，以達到低複雜度之目的。運用polyphase representation將濾波器分解成多個子濾波器。所產生的濾波器，利用CSD乘法器、transposed direct式架構、和CSA以達到高速的要求。此產生器只需要系統規格為了擁有良好的適應性，輸出的程式碼將以可合成的行為階層硬體描述語言撰寫，讓合成工具軟體能依據使用者所指定的條件選擇最適合的架構。
我們提供了一個用於64-QAM基頻解調器的濾波器設計實例。使用Synopsys的合成工具並採用TSMC 0.25μm製程設計晶片。結果在低複雜度應用方面，減少了1.64倍的面積並節省1.95倍的功率消耗。而對於高速應用方面，此晶片能操作在714 MHz。除此之外，我們以此模組產生器設計一個CDMA規格之多階濾波器(IFIR filters)的例子，與傳統濾波器設計相比較，結果減少了1.72倍的硬體面積，節省13.10倍的功率消耗。並且以相同之規格設計一個多階多速率之降頻器，用運IFIR與polyphase representation之設計技巧，與傳統的降頻器設計相比較，結果減少了3.56倍的硬體面積，節省1.96倍的功率消耗。最後，我們還實現一個窄頻的多階多速率之升頻器，與傳統的升頻器設計相比較，結果減少了3.06倍的硬體面積，節省1.36倍的功率消耗。

摘要(英)

In this thesis, a module generator, which can automate the process of designing high-speed low-complexity multirate multistage digital FIR filter / decimator / interpolator, is presented. The generator exploits architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. The input of the generator requires only system-level specifications. In addition, the generator can provide three types of filter structure for different applications. Moreover, the output is a synthesizable Verilog code written in behavioral-level hardware description language (HDL) which allows the synthesis tool to select the appropriate architecture from user’s constraints. Therefore, this tool can eliminate manual calculations, coding, simulation, and verification time of the design cycle.
We have designed several filters with TSMC 0.25μm standard cell. A 64-QAM baseband design example shows that the area is reduced about 1.64 times and the power dissipation is saved about 1.95 times for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Besides, we design the IFIR filters which specification is the first version of the CDMA cellular, the area is reduced about 1.72 times and the power dissipation is saved about 13.10 times as compared with direct form design. An example of multistage decimator used in CDMA cellular shows that the area is reduced about 3.56 times and the power dissipation is saved about 1.96 times as compared with conventional decimator. Finally, an example of the narrowband multistage interpolator are designed, the area is reduced about 3.06 and the power dissipation is saved about 1.36 times as compared with conventional interpolator.

關鍵字(中)

★ 多階多速率系統
★ 數位濾波器
★ 數位降頻器
★ 數位升頻器

關鍵字(英)

★ Multirate Multistage Digital FIR Filter
★ Decimator
★ Interpolator

論文目次

Contents
Chapter 1 Introduction
1.1 Introduction 1
1.2 Motivation and Goals 5
1.3 Thesis Organization 6
Chapter 2 Digital FIR Filter Design
2.1 Basic FIR Filter Design 7
2.1.1 FIR Filter Structure 8
2.1.2 Carry Save Addition 11
2.1.3 Linear Phase FIR Filters 12
2.2 Multiplierless Filter Design 14
2.2.1 CSD Representation 14
2.2.2 CSD Multipliers 17
2.3 RTL Design Technologies for CSD Based Design 18
2.3.1 Sign Extension Elimination 18
2.3.2 Common Subexpression 20
2.3.3 Pipelining 22
Chapter 3 Multirate Multistage Digital FIR Filter Design
3.1 Basic Multirate Operations 24
3.1.1 Decimation 24
3.1.2 Interpolation 27
3.2 The Noble Identities 29
3.3 The Polyphase Representation 30
3.4 Interpolated FIR Filter Design 33
3.5 Multirate Multistage Filter Design 38
Chapter 4 Module Generator Implementation
4.1 System Specifications 41
4.2 Multistage Architecture Analysis 44
4.2.1 Interpolated FIR Filter Decomposition 44
4.2.2 Multirate Multistage FIR Filter Decomposition 49
4.3 Coefficient Calculation 50
4.4 Coefficient Optimization 50
4.4.1 Scaling Strategy 51
4.4.2 Local Search Strategy 54
4.5 Word Length Estimation 55
4.5.1 Overflow Prevention 55
4.5.2 Internal Word Length Reduction 56
4.6 Synthesizable Verilog Code Generation 57
4.6.1 Hardware Estimation 57
4.6.2 Design of the FIR Digital Filter 58
4.6.3 Design of the Interpolated FIR Filter 60
4.6.4 Design of the Multirate Multistage Filter 62
4.7 Module Generator 65
Chapter 5 Experimental Results
5.1 FIR Digital Filter Design 68
5.2 Interpolated FIR Filter Design 74
5.3 Multirate Multistage Filter Design 79
5.3.1 Interpolator 79
5.3.2 Decimator 81
Chapter 6 Conclusions
References

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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2004-7-12

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