應用於三元內容定址記憶體之低功率設計與測試技術

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：73

、訪客IP：52.15.72.229

姓名

林周坤(Chou-Kun Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於三元內容定址記憶體之低功率設計與測試技術
(Low-Power Design and Test Techniques for Ternary Content Addressable Memories)

相關論文

★ 用於隨機存取記憶體的接線驗證演算法	★ 用於降低系統晶片內測試資料之基礎矽智產
★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法	★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試
★ 用於系統晶片中單埠與多埠記憶體之自我修復技術	★ 用於修復嵌入式記憶體之基礎矽智產
★ 自我修復記憶體之備份分析評估與驗證平台	★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計
★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計	★ 低功率與可自我修復之三元內容定址記憶體設計
★ 多核心系統晶片之診斷方法	★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產
★ 應用於貪睡靜態記憶體之有效診斷與修復技術	★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案
★ 應用於隨機存取記憶體之有效良率及可靠度提升技術	★ 應用於特殊半導體記憶體之測試與可靠性設計技術

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

功率消耗和電路面積是三元內容定址記憶的兩個主要設計要點。本論文提供一個10顆電晶體靜態元件和一個三元內容定址記憶體低功率設計方法。我們所提出的10顆電晶體的靜態元件可以以很低的面積費用去實作三元內容定址記憶體。與一個傳統9顆電晶體的靜態二元內容定址記憶體元件比較，我們只需要一個附加電晶體便可實現一個三元內容定址記憶體元件。由實驗結果得知一個10顆電晶體的靜態元件僅僅需要13.83um2面積。同時我們提出一個低功率設計技術，透過把一個字大小的命中線分成若干個疊接小命中線去減少搜尋功率消耗。模擬結果顯示針對一個32 x 64三元內容定址記憶體，當我們分割為８段時，且空白分段比例達到37.5%以上，我們將得到10%~70%功率減少量。
另一方面，由於三元內容定址記憶體的特殊架構使得測試方法更為複雜。所以在本論文中我們發展以實體缺陷為基礎的功能錯誤模型，例如短路缺陷，開路缺陷，電晶體恆開缺陷和電晶體恆關缺陷。我們也提出以功能錯誤模型為基礎的March-like測試演算法。我們的演算法僅僅使用基本的三元內容定址記憶體功能─讀，寫和搜查並且從單一的HIT輸出點去觀察測試結果。我們的演算法針對位元的三元內容定址記憶體僅僅需要4N+2W搜尋操作，4N寫入操作和4N的抹除操作便可偵測100%比較錯誤偵測能力。

摘要(英)

Power dissipation and area cost are two major design concerns of the ternary content addressable memory (TCAM). This thesis presents a 10T static cell and a low-power design methodology for TCAMs. The proposed 10T cell makes a static TCAM be able to be implemented with very low area cost. Compared with a typical 9T static binary cell, only one additional transistor is needed to realize a static ternary cell. Experimental results show that the proposed 10T cell only need about 13.83um2. A low-power design technique is also proposed to reduce the Search power by dividing the match line of a word into multiple cascaded small match lines. Simulation results show that for a 32 x 64 TCAM, about 10%~70% Search power reduction can be achieved if the ratio of empty segments is higher than 37.5% and the segment width is 8.
On the other hand, testing TCAMs is very complicated due to their special structure. In this thesis we develop functional fault models based on physical defects, such as short defects, open defects, transistor stuck-on defects, and transistor stuck-off defects. We also propose a March-like test algorithm for TCAMs based on the proposed functional faults. The test algorithm only requires basic TCAM operations, Write, Search, and Erase, and the test response can be observed entirely from the single-bit Hit output. The test algorithm requires 4N+2W Search operations, 4N Write operations, and 4N Erase operations to cover 100% target comparison faults for an N x W-bit TCAM.

關鍵字(中)

★ 記憶體
★ 低功率
★ 測試
★ 低面積

關鍵字(英)

★ memory
★ testing
★ low power
★ CAM
★ low area
★ TCAM

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Previous Work 2
1.3 Thesis Organization 4
Chapter 2 Overview of Content Addressable Memories 5
2.1 Typical CAM Architecture 5
2.2 CAM Types 7
Chapter 3 Low-Power and Low-Area Design Techniques for TCAMs 13
3.1 Low-Power Design Methodology 13
3.2 The Proposed 10T TCAM Cell 17
3.3 Experimental Results 23
Chapter 4 TCAM Testing 36
4.1 Functional Fault Models 36
4.2 Functional Test Algorithms 53
4.3 Analysis and Comparison 57
Chapter 5 Conclusions 61
Appendix 62
Reference 71

參考文獻

[1] F. Shafai, K.J. Schult, G. F.R. Gibson, A.G. Bluschke, and D.E. Somppi “Fully parallel 30-MHz, 2.5-Mb CAM”, IEEE Journal of Solid-State Circuits, vol. 33, no. 11, pp.1690-1696, Nov.1998.
[2] C.A. Zukowski and Shao-Yi Wang, “Use of selective precharge for low-power content-addressable memories”, in Proc. IEEE Int. Symp. Circuits and Systems, June 1997, pp. 1788-1791.
[3] T. Juan, T. Lang, and J.J. Navarro, “Reducing TLB power requirements”, in Proc. IEEE Int. Symp. Low Power Electronics and Design, Aug. 1997, pp.196 – 201.
[4] K.-J. Lin and C.-W. Wu, “A low-power CAM design for LZ data compression”, IEEE Trans. Computers, vol. 49, no.10, pp. 1139 – 1145, Oct. 2000
[5] G. Thirugnanam, N. Vijaykrishnan, and M.J. Irwin, “A novel low power CAM design”, in Proc. IEEE ASIC/SOC Conference, Sept. 2001, pp. 198 – 202.
[6] Y.-L. Hsiao, D.-H. Wang, and C.-W. Jen, “Power modeling and low-power design of content addressable memories”, in Proc. IEEE Int. Symp. Circuits and Systems, May 2001, pp. 926 – 929.
[7] H. Miyatake, M. Tanaka, and Y. Mori,” A design for high-speed low-power CMOS fully parallel content-addressable memory macros”, IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 956 – 968, June 2001.
[8] C.-S. Lin, J.-C. Chang, and B.-D. Liu, “A low-power precomputation-based fully parallel content-addressable memory”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp.654-662, Apr. 2003.
[9] I. Arsovski, T. Chandler, and A. Sheikholeslami, “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme”, IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 155 – 158, Jan. 2003.
[10] G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda “200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme”, in Proc. IEEE Custom Integrated Circuits Conference, Sept. 2003, pp. 387 – 390.
[11] I. Arsovski and A. Sheikholeslami, “A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories”, IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp.1958-1966, Nov. 2003.
[12] T. Chadwick, T. Gordon, R. Nadkarni, J. Rowland “An ASIC-embedded content addressable memory with power-saving and design for test features”, IEEE Custom Integrated Circuits Conference, May. 2001, pp. 183 – 186.
[13] S. Jones, “Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture”, in Proc. IEEE Computers and Digital Techniques, vol. 135, no. 3, pp. 165 – 172, May 1988.
[14] S.R. Ramirez-Chavez, “Encoding don't cares in static and dynamic content-addressable memories”, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol.39, no. 8, pp. 575-578, Aug. 1992.
[15] Inc. MOSAID Technologies, “The next generation of content addressable memories”, http://www.mosaid.com/, 1999.
[16] V. Lines, A. Ahmed, P. Ma, S. Ma, R. McKenzie, H.-S. Kim, and C. Mar, “66 MHz 2.3 M ternary dynamic content addressable memory”, IEEE Int. Workshop on Memory Technology, Design and Testing, Aug. 2000, pp. 101-105.
[17] W. K. Al-Asssdi, A. P. Jayasumana, and Y. K. Malliya, “On fault modeling and testing of content-addressable memories”, Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, Aug. 1994, pp. 78-83.
[18] P. R. Sidorowicz and J. A. Brzozowski, “An approach to modeling and testing memories and its application to CAMs”, Proc. IEEE VLSI Test Symp. (VTS), Apr. 1998, pp. 411-416.
[19] P. R. Sidorowicz, “Modeling and testing transistor faults in content-addressable memories”, Record of IEEE Int. Workshop on Memory Technology, Design and Testing, Aug. 1999, pp. 83-90.
[20] K. J. Lin and C.-W. Wu, “Testing content-addressable memories using functional fault models and march-like algorithms”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, no. 5 , pp. 577 – 588, May 2000.
[21] J. Zhao, S. Irrinki, M. Puri, and F. Lombardi, ”Testing sram-based content addressable memories ”, IEEE Trans. Computer, vol. 49, no. 10, pp. 1054 – 1063, Oct. 2000.
[22] P. R. Sidorowicz and J. A. Brzozowski, “A framework for testing special-purpose memories”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, no. 12 , pp. 1459 - 1468, Dec. 2002.
[23] D. Wright and M. Sachdev, “Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories”, Proc. Int. Test Conference (ITC), Sept. 30-Oct. 2003, pp. 39 – 47.
[24] J.G. Delgado-Frias, A. Yu, and J. Nyathi, “A dynamic content addressable memory using a 4-transistor cell”, Proc. Int. Workshop on Design of Mixed-Mode Integrated Circuits and Applications, 26-28 July 1999, pp. 110 – 113.
[25] P. Lin and J. Kuo, “A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell”, IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp.666-676, Apr. 2001.
[26] J.-F. Li, R.-S. Tzeng and C.-W. Wu, “Testing and diagnosis methodologies for embedded content addressable memories”, J. Electronic Testing: Theory and Application, vol.19, no.2, pp. 207-215, Apr. 2003.

指導教授

李進福(Jin-Fu Li)

審核日期

2004-7-15

推文