自我修復記憶體之備份分析評估與驗證平台

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姓名

張達銘(Da-Ming Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

自我修復記憶體之備份分析評估與驗證平台
(An Evaluation and Verification Platform for Built-In Redundancy Analysis Schemes of Self-Repairable Memories)

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摘要(中)

嵌入式記憶體是現今系統晶片中最常被使用到核心。根據2001年International Technology Roadmap for semiconductor (ITRS)，現今系統晶片中，超過50%晶片面積會被嵌入式記憶體所佔據。所以當嵌入式記憶體有缺陷(defect)發生時，會大幅的降低整體系統晶片的製造良率。所以對於系統晶片良率的提升，可修復的嵌入式記憶體扮演一個重要腳色。為了降低實現可修復的嵌入式記憶體所必須付出的代價，可以利用內建式自我測試與內建式備份分析去實現低成本的可修復的嵌入式復記憶體。由於嵌入式記憶體中的備份元件的使用效率取決於備份分析的演算法，所以如何快速地找到一個有效並且經濟的備份分析的演算法是重要的。
在這篇論文中，提出一個平台可以幫助使用者評估所提出的內建式備份分析演算法的好壞並且進一步去驗證所設計的電路功能是否符合所推導的備份分析的演算法。在平台中可以依據使用者所訂的記憶體一些參數與備份元件的種類與數量去評估出備份分析的演算法在這樣的狀態下的修復率。進一步可以分析壞掉的記憶體在測試機台所產生的錯誤資訊(fail log file)在這樣的備份分析的演算法錯誤的記憶體是否可以修復。針對驗證備份分析演算法的實現電路方面，這個平台能夠產生測試樣本(test pattern)去驗證它的功能是否與所推導的備分分析的演算法相同並且正確。除此之外我們針對可修復的記憶體擁有備份行、備份列與備份字元提出一個備份分析的演算法，利用所建立的平台去做分析，這個演算法在記憶體大小為，並且擁有一個備份列(一個備份列可視為128個備份字元組)、兩個備份行與兩個備份字元作修復率分析時，其修復率可相同於最佳的備份分析的演算法(Exhaustive Algorithm)在相同的記憶體大小、錯誤分佈與錯誤狀態但其擁有三個備份列與兩個備份行。針對的記憶體且擁有三個備份列、三個備份行與兩個備份字元，利用此演算法將完整的BIRA電路實現出來只增加了2.01%的記憶體面積。

摘要(英)

Embedded memory is one of the most widely used cores in system-on-chips (SoCs). According to the 2001 International Technology Roadmap for Semiconductor (ITRS), the embedded memories currently occupy more than 50% of the system on chips (SoCs). The defects in the embedded memory arrays can significantly degrade manufacturing yield. So the repairable embedded memories play an important role for the improvement of SoC yield. To reduce the cost of the repairable embedded memory implementation, the repairable embedded memories are implemented by built-in self-test (BIST) and built-in redundancy-analysis (BIRA). The efficiency of the redundancy depends on the RA algorithm. Thus it is important to find an efficient and economical RA algorithm rapidly.
In this thesis, we present a platform for the evaluation and verification of BIRAs. It can calculate the repair rate with respect to the specification of the memory and the spare element or the information from the fail log file. The platform can generate the test benches for the BIRA functional verification. We also propose an efficient RA algorithm for a memory with spare rows, spare columns, and spare words. Simulation results show that the repair rate of the proposed RA algorithm for an -bit memory with one spare row (one spare row = 128 spare words), two spare columns, and two spare words is the same as the repair rate of the exhaustive RA algorithm for the same memory with three spare rows and two spare columns. The area cost of the proposed BIRA architecture is only 2.01% of an -bit memory with three spare rows, three spare columns and two spare words.

關鍵字(中)

關鍵字(英)

★ evaluation
★ verification
★ platform
★ BIRA
★ BISR
★ built-in redundancy analysis scheme

論文目次

Chapter 1 Introduction 1
Chapter 2 Evaluation and Verification Platform for BIRA Designs 3
2.1 Evaluation and Verification of BIRA 3
2.2 Selection of the Redundancy Type 7
2.3 Selection of the Memory Type and Architecture 8
2.4 Specified Fault Map Generation 10
2.5 Random Fault Map Generation 10
2.5.1 Defect Injection 10
2.5.2 Fault Distribution 12
2.5.3 Fault Map Generation and Test Algorithm Simulation 18
2.6 Function Selection 26
2.7 Comparison 30
Chapter 3 An Efficient Redundancy Analysis Algorithm 33
3.1 Proposed Redundancy Analysis Algorithm 33
3.2 Local Bitmap 35
3.3 Rules of Redundancy Analysis 36
3.4 BIRA Implementation 41
3.5 Experimental Results 44
Chapter 4 Conclusions and Future Work 48
4.1 Conclusions 48
4.2 Future Work 48
Appendix 50
Reference 55

參考文獻

[1] SIA. Semiconductor industry association, international technology roadmap for semiconductors: Design. http://public.itrs.net/Files/2001ITRS/design.pdf, 2001.
[2] S.-Y. Kuo and W.-K. Funchs, “Efficient spare allocation in reconfigurable arrays”, in Proc. Design Automation and Test in Europe, 1986, pp. 385-390.
[3] S.-Y. Kuo and W.-K. Funchs, “Efficient spare allocation in reconfigurable arrays”, IEEE Design and Test of Computer, 1987, pp. 385-390.
[4] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs”, in Proc. International Test Conference, Oct. 2000, pp. 567-574.
[5] D.-K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264”, in Proc. International Test Conference, Sept. 1999, pp. 311-318.
[6] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement”, IEEE Tran. Reliability, vol. 52, no. 4, Dec. 2003, pp. 389-399.
[7] Y.-N. Shen, N. Park, and F. Lombardi, “Spare cutting approaches for repairing memories”, in Proc. IEEE Int. Conf., Oct. 1996, pp. 106-111.
[8] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair scheme for semiconductor memories with 2-d redundancy”, in Proc. Internal Test Conference, Sept. 2003, pp. 393-402.
[9] S.-K. Lu and C. Hsu, “Built-In Self-Repair for Divided Word Line Memory”, in Proc. IEEE International Symposium on Circuit and Systems (ISCAS), May 2001, vol.4, pp. 13-16.
[10] R.-F. Hung, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, ‘Fail Pattern Identification for Memory Built-In Self-Repair’, in Proc. The 13th Asian Test Symposium, Nov. 2004, pp. 366-371.
[11] M. Nicolaidis, N.Achouri, and S.Boutobza, ‘Optimal reconfiguration functions for column or data-bit built-in self-repair’, in Proc. Design Automation and Test in Europe, Munich, Mar. 2003, pp. 590-595.
[12] M. Nicolaidis, N.Achouri, and S.Boutobza, ‘Dynamic data-bit memory built-in self-repair’, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2003, vol. 51, no. 1, pp. 588-594.
[13] M. Horiguchi, J. Etoh, M. Aoki, K. Itoh, and T. Matsumoto, “A flexible redundancy technique for high-density DRAM’s”, IEEE Journal of Solid-State Circuits, Jan. 1991, vol. 26, no. 1, pp. 12-17.
[14] X. Du, S.M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed built-in self-repair analyzer for embedded word-oriented memories”, in Proc. 17th International Conference on VLSI Design, 2004, pp. 895-900.
[15] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F.-P. Higgins, and J.-L. Lewandowski, “Built in self repair for embedded high density SRAM”, in Proc. International Test Conference, Oct. 1998, pp. 1112-1119.
[16] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm”, in Proc. International Test Conference, Sept. 1999, pp. 301-310.
[17] Y. Nagura, M. Mullins, A. Sauvageau, Y. Fujiwara, K. Furue, R. Ohmura, T. Komoike, T. Okitaka, T. Tanizaki, K. Dosaka, K. Arimito, Y. Koda, and T. Tada, “Test cost reduction by at-speed BISR for embedded DRAMs”, in Proc. International Test Conference, Nov. 2001, pp 182-187.
[18] C. L. Wey and Lombardi, “On the repair of redundant RAM’s”, IEEE Trans. on Computer-Aided Design, 1987, vol. CAD-6, pp. 222-231.
[19] S.-K. Lu, “Built-in self-repair techniques for embedded RAMs”, IEE Proc. Computers & Digital Techniques, July 2003, vol. 150, no. 4, pp. 201-208.
[20] R. McConnel, R. Rajsuman, E. Nelson, and J. Dreibelbies, “Test and repair of large embedded DRAMs: Part 1”, in Proc. International Test Conference, 2001, pp. 163-172.
[21] E. Nelson, J. Dreibelbies, R. McConnel,“Test and repair of large embedded DRAMs: Part 2”, in Proc. International Test Conference, 2001, pp. 173-181.
[22] T. Chen and G. Sunada, “A self-testing and self-repairing structure for ultra large capacity memories”, in Proc. International Test Conference, 1992, pp.623-631.
[23] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories”, in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, July 2002, pp. 68-73.
[24] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories”, in Proc. The Eighth IEEE Int. On-Line Testing Workshop, July 2002, pp. 262-267.
[25] A. Sehgal, A. Dubey, E.-J. Marinissen, C. Wouters, H. Vranken, and K. Chakrabarty, “Yield analysis for repairable embedded memories”, in Proc. IEEE European Test Workshop, May 2003, pp. 35-40.
[26] A. Sehgal, A. Dubey, E.-J. Marinissen, C. Wouters, H. Vranken, and K. Chakrabarty, “Redundancy modeling and array yield analysis for repairable embedded memories”, IEE Computer and Digital Techniques, Jan. 2005, pp. 97-106.
[27] M.-L. Bushnell and V.-D. Agrawal. Essentials of Electronic testing for Digital Memory and Mixed-Signal VLSI. Kluwer Academic Publishers, Norwell, Massachusetts, 2000.

指導教授

李進福(Jin-Fu Li)

審核日期

2005-11-14

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