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姓名	蘇嘉偉(Chia-Wei Su)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	責任週期調整與時脈同步電路之設計與實現 (Design and Implementation of Duty Cycle Adjustment and Clock Synchronization Circuits)
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摘要(中)	隨著系統晶片(System-on-Chip, SoC)在速度的效能上快速的增加，時脈偏斜所造成時脈不同步現象而嚴重威脅系統運作的正確性，因此有許多相位同步之電路常被用以校正時脈歪斜(skew)，如鎖相迴路(PLL)、延遲迴路(DLL)及同步延遲迴路(SMD)等。然而除了時脈訊號同步的問題外，時脈訊號之責任週期(Duty Cycle)也需要被精準的控制，以提高電路操作之可靠度、正確性。在雙倍取樣的系統中，如雙緣取樣之靜態記憶體與類比數位轉換器，精準50%責任週期的時脈變得相當重要。因此，有許多責任週期校正電路使用於系統晶片中，如責任週期校正器(Duty Cycle Corrector, DCC)及脈波寬度控制迴路(PulseWidth Control Loop, PWCL)。 首先本論文提出一個具高線性控制、快速鎖定及寬頻操作與輸出週期可程式化之脈波寬度控制迴路，此電路使用電路偵測達到鎖定時間在650ns以內，並使用頻率偵測器控制多級高線性度之控制單元使所提出之電路可以在寬頻率與寬輸入責任週期範圍內亦可正常穩定操作，其可操作輸入責任週期範圍與頻率範圍分別為30%~70%及1MHz~1.3GHz。為了延伸系統晶片中各種電路之應用，此電路可用數位程式化控制輸出責任週期，其輸出範圍為30%~70%以每5%為一單位。新式的控制單元配合多級控制單元、頻率偵測器及責任週期偵測器可以達到高線性度且大範圍操作。在新式的脈波寬度控制迴路中的數位控制充電幫浦可以輸出多種不同的責任週期。其可以輸出之責任週期為30%~70%，以5%為一單位。此測試電路使用0.18μm製程製作及量測驗証。 接著本論文針對系統晶片中許多電路需要快速鎖定的時脈同步電路，而提出寬頻同步延遲複製電路，此電路使用頻率偵測器控制多段延遲偵測電路，使其可操作頻率可延伸至200MHz~1GHz。使用多段頻率控制，鎖定週期可以降到最多為8個週期。所提出電路中使用相位微調，來校正在各個電路中可能產生之相位誤差，其最大相位為6.7ps。在此電路並使用DFF-based的MCC來達到輸入責任週期可以在任意責任週期下正常操作，而其責任週期範圍在200MHz為10%~90%。為了達到節省功率，此電路在不同頻率下關閉不需使用之電路進而達到功率節省，使用此方法最大節省功率可達40%。 最後本論文針對系統晶片對於相位同步與責任週期校正之需要，結合了前兩個電路之優點，提出具寬頻操作及可程式化責任週期之數位同步電路，以全數位的同步複製延遲電路達到時脈同步功能，並以先前提出之寬頻可程式化之脈波寬度控制迴路來校正及程式化時脈責任週期，進而達到時脈同步且責任週期可程式化之功能。在所提出之電路中使用頻率偵測器控制多段延遲線達到縮減電路面積、較寬的操作頻率以及節省功率消耗的效果，並使用單擊電路取代原始輸入緩衝器，使提出之數位同步電路的輸入責任週期範圍增加至5%~97%。具寬頻操作及可程式化責任週期之數位同步電路使用0.18μm製程製作，其操作頻率能夠操作在160MHz~800MHz之間且輸出責任週期可由數位程式控制從35%到70%以5%為一單位。此電路完成相位及脈波寬度鎖定時間小於250ns，鎖定後相位誤差小於21ps及責任週期誤差小於±1%。所提出電路之功率消耗在600MHz時為12.8mW，比未加省電機制時減少了35.9%，核心面積約為0.067mm2。 在本論文中所提出之三個時脈電路可以讓系統晶片之時脈網路在運用時更具有彈性及強健性，可以針對系統中不同之需求使用此三種時脈電路。
摘要(英)	With the increasing operating frequency in SoC, the clock skew would serious cause the incorrect system operation. Therefore, many synchronous circuits use to align clock skew, for example phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror delay circuits (SMD) and etc. However, except the clock skew problem, clock duty cycle also needs to be accurate controlled to improve the reliability and correctness of circuits. In the double sampling system, the exact 50% clock duty cycle becomes quite important, for example double-sample rate SDRAM or double-sample rate ADC. Therefore, many clock duty cycle alignment circuits use in SoC, for example duty cycle corrector (DCC) and pulse width control loop (PWCL). First, this dissertation proposed a high linearity, fast-locking pulse width control loop with digitally programmable duty cycle correction for wide range operation. This circuit uses error amplifier to detect and achieve fast locking within 650ns. Using frequency detector to control multi-stage control stages, the proposed PWCL can stable operated within a wide-range of both input and output duty cycles over a wide frequency range. It can be operated with a frequency range from 1MHz to 1.3GHz and the duty cycle range of the input signal is from 30% to 70%. To extend the circuit application in SoC system, the proposed PWCL can use digital program to control output duty cycle, which the output duty cycle range is from 30% to 70% in step of 5%. This experimental chip has been fabricated using 0.18 μm CMOS process. Next, we developed a wide-range synchronous mirror delay with arbitrary input duty cycle for some clock synchronous circuits which need fast locking in SoC. The proposed wide-range SMD uses frequency detector to control multi-band delay monitor circuit to extend the operation frequency range which is from 200MHz to 1GHz. Using frequency selection scheme, the maximum locking cycle can be reduced to eight clock cycles. The fine tune circuit uses to calibrate the delay mismatch of each circuit and the maximum phase error is 6.7ps. The DFF-based MCC uses to correct operation in arbitrary input duty cycle and its duty cycle range at 200MHz is from 10% to 90%. To reduce power consumption, the proposed circuit would disable the non-operation circuit to achieve power saving and the maximum saving power is up to 40%. Finally, this dissertation aims at both demands of phase synchronization and duty cycle alignment to propose a wide-range digital synchronous buffer (DSCB) with digitally programmable output duty cycle. The digital synchronized delay circuit with SMD solves the long tracking time problem of PLL and DLL. The output duty cycle can be corrected and programmed by the high linearity PWCL. Using frequency detector, the multi-band delay lines are used to reduce the chip area, widen the operation frequency and save power consumption. The input buffer of the proposed SMD uses one-shot circuit to achieve the proposed wide-range digital synchronous buffer to accept wide input duty cycle range from 10% to 90%. The proposed synchronous buffer with programmable duty cycle has been fabricated using 0.18μm CMOS 1.8V process. The measurement results show that the operation frequency range is form 160MHz to 800MHz, the input duty cycle range is from 5% to 97%, and the preset output duty cycle range is form 35% to 70% in steps of 5%. The locking time is less than 250ns when phase and duty cycle are both locked. The phase error is less than 21ps and the duty cycle error is less than ±1%. The power consumption is 12.8mW in 600MHz with save power mode that is less than normal mode about 35.9%. The core area is about 0.067mm2. In the dissertation, we proposed three clocking alignment circuits to let the application in SoC clock distribution network have more flexible and robust and use in different demand.
關鍵字(中)	★ 寬頻操作 ★ 快速鎖定 ★ 責任週期校準器 ★ 時脈同步電路 ★ 同步延遲電路 ★ 脈波寬度控制迴路	關鍵字(英)	★ duty cycle adjustment ★ clock synchronous circuit
論文目次	摘要 I Abstract III 誌謝 VII Contents VIII Figure Captions XIII Table Captions XX Chapter 1 Introduction 1 1.1. Demand for Clocking System 1 1.2. Overview of the Dissertation 5 Chapter 2 Fundamentals of Duty Cycle Adjustment and Clock Synchronization Circuits 7 2.1. Duty Cycle Alignment Circuits 7 2.1.1. Open Loop Architecture 8 2.1.2. Close Loop Architecture 9 2.2. Clock Synchronization Circuits 11 2.2.1. Close-Loop Architecture 12 2.2.2. Open-Loop Architecture 16 Chapter 3 Highly Linear and Fast Locking Pulse Width Control Loop 19 3.1. Architecture of Conventional Pulse Width Control Loops 19 3.1.1. Original Pulse Width Control Loop 19 3.1.2. Low-Voltage Pulse Width Control Loop 20 3.1.3. Fast-Locking Pulse Width Control Loop 21 3.1.4. Mutual-Correlated Pulse Width Control Loop 21 3.1.5. Signle-Path Pulse Width Control Loop 22 3.2. High-Linearity Pulse Width Control Loop 23 3.2.1. Multi-Stage Control Stage 26 3.2.2. Frequency Detector (FD) 27 3.2.3. Duty Cycle Detector (DCD) 29 3.2.4. Digital Controlled Charge Pump (DCCP) 31 3.3. Simulation and Comparison Results 33 3.3.1. Conventional CS versus Proposed CS 33 3.3.2. Differential Output Phase Error 35 3.3.3. Fast-Locking Simulation 36 3.3.4. Different Output Duty Cycle 37 3.3.5. Wide-Range Operation 38 3.3.6. Monte Carlo Analysis 39 3.4. Proposed PWCL Design 42 3.4.1. Behavior Linear Model 42 3.4.2. Transient Response 45 3.5. Measurement Environment Setup and Experiment Results 47 3.5.1. Concept 47 3.5.2. Measurement Environment Setup 47 3.5.3. Experiment Results 49 Chapter 4 Wide-Range Synchronous Mirror Delay with Arbitrary Input Duty Cycle 55 4.1. Architecture of Conventional Synchronous Mirror Delays 55 4.1.1. Original Synchronous Mirror Delay 55 4.1.2. Interleaved Synchronous Mirror Delay 57 4.1.3. Direct-Skew-Detect Synchronous Mirror Delay 58 4.1.4. Mixed-mode Synchronous Mirror Delay 59 4.1.5. Successive Approximation Register Synchronous Mirror Delay 60 4.1.6. Arbitrary Duty Cycle Synchronous Mirror Delay 61 4.2. Wide-Range Synchronous Mirror Delay 62 4.2.1. Proposed SMD Architecture 62 4.2.2. Timing and Operation Analysis 63 4.3. System Analysis 66 4.3.1. Linear Model Analysis 66 4.3.2. Behavior Model Analysis 68 4.4. Simulation Results 69 Chapter 5 Wide-Range Digital Clock Synchronous Buffer with Digitally Programmable Output Duty Cycle 75 5.1. Wide-Range Digital Clock Synchronous Buffer 75 5.1.1. Pulse Width Generator (PWG) 79 5.1.2. Multi-Band Delay Monitor Circuit (MB-DMC) 80 5.1.3. Measurement and Mirror Circuit (MMC) 81 5.1.4. Phase Compensation Circuit (PCC) 82 5.1.5. Frequency Phase Comparator (FPC) 82 5.1.6. Modified Pulse Width Control Loop (PWCL) 85 5.2. System Analysis and Simulation Results 88 5.2.1. Different Phase Alignment Comparison 88 5.2.2. Stage Length of Delay Line Analysis 89 5.2.3. Locking Time Analysis 90 5.2.4. Dynamic frequency hopping 90 5.2.5. Different Output Duty Cycle 92 5.2.6. Jitter Induced and Ground Bounce Simulation 93 5.3. Measurement Environment Setup and Experiment Results 95 5.3.1. Concept 95 5.3.2. Measurement Environment Setup 95 5.3.3. Experimental Results 97 Chapter 6 Conclusions and Future Works 103 6.1. Conclusion 103 6.2. Future Work 105 Reference 107 Publication List 113
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指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2008-11-14
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