多重相位之延遲鎖定迴路倍頻器設計與分析

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姓名

張書銘(Shu-Ming Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

多重相位之延遲鎖定迴路倍頻器設計與分析
(Design and Analysis of Multiphase DLL-based Frequency Multipliers)

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摘要(中)

因為容易設計及穩定的特性，延遲鎖定迴路(Delay-Locked Loop)已經比鎖相迴路(Phase-Locked Loop)更廣泛地應用在時脈誤差調整上。不僅如此，在現今有越來越多的應用開始使用延遲鎖定迴路，例如本地震盪電路與時脈產生器，而這一些應用在以前只能使用鎖相迴路。因此，在不久的未來，延遲鎖定迴路將會更加重要
在本論文中主要針對延遲鎖定迴路及其多重相位倍頻器與差動倍頻器作出說明以及討論，並且使用TSMC 0.18μm 1P6M CMOS Process，供應電壓為1.8V；設計出一個1.28GHz延遲迴路倍頻器。其延遲鎖定迴路的輸入範圍為220MHz~320MHz，多重相位倍頻器輸出時脈倍數可利用數位信號控制來達成，頻率倍數為1x、2x及4x；另外差動倍頻器則會直接合成出2x及4x的訊號。輸出頻率為220MHz ~ 320MHz (1倍頻)、440MHz ~ 640MHz (2倍頻)、880MHz ~ 1.28GHz (4倍頻)，電路操作於1.0GHz輸出時脈之峰對峰擾動值分別為32.7ps與54.49ps，其功率消耗為67.16mW。

摘要(英)

Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as local oscillator and clock generator where only used with PLL in the past and are employed DLLs. So, the DLLs will be more significant in the near future.
The main object of this thesis is the description and discussion in Delay-Locked Loop, multiphase edge combiner and fully differential edge combiner; uses TSMC 0.18μm 1P6M CMOS process to design a 1.28GHz DLL-based frequency multiplier and the supply voltage is 1.8V. The operate frequency range of DLL is 220MHz to 329MHz; the multiple factor of the multiphase edge combiner can easily use with digital control code and the multiple factor is 1x, 2x and 4x. Besides, the fully differential edge combiner can directly synthesize the 2x and 4x output signals. The synthesized frequencies of the DLL-based frequency multiplier are 220MHz to 320MHz (multiply-by-1), 440MHz to 640MHz (multiply-by-2) and 880MHz to 1.28GHz (multiply-by-4). The power dissipation and peak-to-peak jitters are 67.16mW and 32.7ps, 54.49ps at 1.0GHz output clock frequency.

關鍵字(中)

★ 延遲鎖定迴路
★ 倍頻器

關鍵字(英)

★ Delay-Locked Loop
★ frequency multiplier

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Research Goals 2
1.3 Thesis Organization 3
Chapter 2 Background of Frequency Synthesizer 5
2.1 Architecture of Frequency Synthesizer 5
2.1.1 Direct Digital Frequency Synthesis 5
2.1.2 PLL-based Frequency Synthesizer 6
2.1.3 DLL-based Frequency Synthesizer 8
2.2 Phase-Locked Loop 9
2.2.1 Phase-Locked Loop Fundamental 10
2.2.2 Linear Model Analysis of PLL 11
2.3 Delay-Locked Loop 12
2.3.1 Delay-Locked Loop Fundamental 13
2.3.1.1 Phase Detector 14
2.3.1.2 Charge Pump (CP) and Loop Filter (LF) 15
2.3.1.3 Voltage-Controlled Delay Line (VCDL) 16
2.3.2 Stability Analysis of Delay-Locked Loop 17
2.3.3 Design Consideration of the Delay-Locked Loop 18
2.3.4 Applications of DLL-based Frequency Synthesizer 20
2.3.4.1 Frequency Multiplier for RF Front End 20
2.3.4.2 Frequency Multiplier for High Speed Serial Link 21
2.4 The Comparison of PLL/DLL-based Frequency Synthesizer 22
2.4.1 The basic of DLL-based Frequency Multiplier 23
2.4.1.1 Operation of DLL-based Frequency Multiplier 23
2.4.2 Timing Jitter Accumulation 25
Chapter 3 The Analysis of DLL-based Frequency Multiplier 28
3.1 Introduction 28
3.2 Performance Analysis 28
3.2.1 Phase Noise 29
3.2.1.1 Timing Jitter Accumulation 30
3.2.1.2 Power Spectral Density of Timing Error Random Process 33
3.2.2 Spurious Tones 35
3.2.2.1 Delay Mismatch 35
3.2.2.2 Static Phase Error 36
3.3 Performance Implications for Communication Systems 38
3.3.1 Phase Noise 38
3.3.2 Spurious Tones 40
3.4 The Development of DLL-based Frequency Multiplier 41
3.4.1 Local Oscillator for PCS Applications 42
3.4.2 Frequency Multiplier for Clock Multiplication 43
3.4.3 DLL-based Clock Synthesizer and Tunable Oscillator 44
3.4.4 Programmable DLL-based Frequency Multiplier 46
3.4.5 Low Power Small Area DLL-based Clock Generator 48
Chapter 4 The Programmable DLL-based Frequency Multiplier 50
4.1 Introduction 50
4.2 The Programmable Multiphase DLL-based Frequency Multiplier in High Speed Serial Link Application 50
4.2.1 The Basic Idea of Programmable Multiphase DLL-based Frequency Multiplier 52
4.3 Architecture of Programmable Multiphase DLL-based Frequency Multiplier 55
4.3.1 Phase Selector and Multiphase Edge Combiner 56
4.3.2 Phase Detector 57
4.3.3 Charge Pump and Loop Filter 59
4.3.4 Voltage-Controlled Delay Line 61
4.4 Simulation Results 63
4.5 Conclusion 64
Chapter 5 The Fully Differential DLL-based Frequency Multiplier 66
5.1 Introduction 66
5.2 The Fully Differential DLL-based Frequency Multiplier in Wireless Communication System Application 67
5.2.1 The Theory of Fully Differential DLL-based Frequency Multiplier 68
5.3 Architecture of Fully Differential DLL-based Frequency Multiplier 70
5.3.1 Fully Differential Edge Combiner and Duty Cycle Corrector 71
5.3.2 Phase Detector 73
5.3.3 Charge Pump and Loop Filter 74
5.3.4 Voltage-Controlled Delay Line 75
5.4 Simulation Results 79
5.5 Conclusion 81
Chapter 6 Chip Implementationt 83
6.1 Introduction 83
6.2 The Concept of Signal Integrity 83
6.2.1 Termination 84
6.2.2 The Output Interface of LVDS Driver 86
6.2.2.1 Single-Ended Trans-Impedance Amplifier (TIA) 86
6.2.2.2 Digitalize LVDS Driver 87
6.3 Chip Overview 89
6.4 Experimental results 91
Chapter 7 Conclusion 95
References 97

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2005-7-16

推文